From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932264AbcDGSDa (ORCPT ); Thu, 7 Apr 2016 14:03:30 -0400 Received: from mail.kernel.org ([198.145.29.136]:60315 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932179AbcDGR5b (ORCPT ); Thu, 7 Apr 2016 13:57:31 -0400 Date: Thu, 7 Apr 2016 12:57:25 -0500 From: Rob Herring To: Chen-Yu Tsai Cc: Maxime Ripard , Florian Fainelli , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, LABBE Corentin Subject: Re: [PATCH RFC 1/5] net: phy: sun8i-h3-ephy: Add bindings for Allwinner H3 Ethernet PHY Message-ID: <20160407175725.GG32257@rob-hp-laptop> References: <1459786954-12649-1-git-send-email-wens@csie.org> <1459786954-12649-2-git-send-email-wens@csie.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1459786954-12649-2-git-send-email-wens@csie.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 05, 2016 at 12:22:30AM +0800, Chen-Yu Tsai wrote: > The Allwinner H3 SoC incorporates an Ethernet PHY. This is enabled and > configured through a memory mapped hardware register. > > This same register also configures the MAC interface mode and TX clock > source. Also covered by the register, but not supported in these bindings, > are TX/RX clock delay chains and inverters, and an RMII module. > > Signed-off-by: Chen-Yu Tsai > --- > .../bindings/net/allwinner,sun8i-h3-ephy.txt | 44 ++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-h3-ephy.txt Acked-by: Rob Herring From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH RFC 1/5] net: phy: sun8i-h3-ephy: Add bindings for Allwinner H3 Ethernet PHY Date: Thu, 7 Apr 2016 12:57:25 -0500 Message-ID: <20160407175725.GG32257@rob-hp-laptop> References: <1459786954-12649-1-git-send-email-wens@csie.org> <1459786954-12649-2-git-send-email-wens@csie.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: Mark Rutland , devicetree@vger.kernel.org, Florian Fainelli , Pawel Moll , Ian Campbell , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, LABBE Corentin , Kumar Gala , Maxime Ripard , linux-arm-kernel@lists.infradead.org To: Chen-Yu Tsai Return-path: Content-Disposition: inline In-Reply-To: <1459786954-12649-2-git-send-email-wens@csie.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org List-Id: netdev.vger.kernel.org On Tue, Apr 05, 2016 at 12:22:30AM +0800, Chen-Yu Tsai wrote: > The Allwinner H3 SoC incorporates an Ethernet PHY. This is enabled and > configured through a memory mapped hardware register. > > This same register also configures the MAC interface mode and TX clock > source. Also covered by the register, but not supported in these bindings, > are TX/RX clock delay chains and inverters, and an RMII module. > > Signed-off-by: Chen-Yu Tsai > --- > .../bindings/net/allwinner,sun8i-h3-ephy.txt | 44 ++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-h3-ephy.txt Acked-by: Rob Herring From mboxrd@z Thu Jan 1 00:00:00 1970 From: robh@kernel.org (Rob Herring) Date: Thu, 7 Apr 2016 12:57:25 -0500 Subject: [PATCH RFC 1/5] net: phy: sun8i-h3-ephy: Add bindings for Allwinner H3 Ethernet PHY In-Reply-To: <1459786954-12649-2-git-send-email-wens@csie.org> References: <1459786954-12649-1-git-send-email-wens@csie.org> <1459786954-12649-2-git-send-email-wens@csie.org> Message-ID: <20160407175725.GG32257@rob-hp-laptop> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Apr 05, 2016 at 12:22:30AM +0800, Chen-Yu Tsai wrote: > The Allwinner H3 SoC incorporates an Ethernet PHY. This is enabled and > configured through a memory mapped hardware register. > > This same register also configures the MAC interface mode and TX clock > source. Also covered by the register, but not supported in these bindings, > are TX/RX clock delay chains and inverters, and an RMII module. > > Signed-off-by: Chen-Yu Tsai > --- > .../bindings/net/allwinner,sun8i-h3-ephy.txt | 44 ++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-h3-ephy.txt Acked-by: Rob Herring