From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754615AbcDKPDw (ORCPT ); Mon, 11 Apr 2016 11:03:52 -0400 Received: from mail.kernel.org ([198.145.29.136]:53549 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753318AbcDKPDu (ORCPT ); Mon, 11 Apr 2016 11:03:50 -0400 Date: Mon, 11 Apr 2016 10:03:44 -0500 From: Rob Herring To: Roger Quadros Cc: tony@atomide.com, computersforpeace@gmail.com, boris.brezillon@free-electrons.com, dwmw2@infradead.org, ezequiel@vanguardiasur.com.ar, javier@dowhile0.org, fcooper@ti.com, nsekhar@ti.com, linux-mtd@lists.infradead.org, linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 15/17] memory: omap-gpmc: Support WAIT pin edge interrupts Message-ID: <20160411150344.GA3549@rob-hp-laptop> References: <1460023715-19332-1-git-send-email-rogerq@ti.com> <1460023715-19332-16-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1460023715-19332-16-git-send-email-rogerq@ti.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 07, 2016 at 01:08:33PM +0300, Roger Quadros wrote: > OMAPs can have 2 to 4 WAITPINs that can be used as edge triggered > interrupts if not used for memory wait state insertion. > > Support these interrupts via the gpmc IRQ domain. > > The gpmc IRQ domain interrupt map is: > > 0 - NAND_fifoevent > 1 - NAND_termcount > 2 - GPMC_WAIT0 edge > 3 - GPMC_WAIT1 edge, and so on > > Signed-off-by: Roger Quadros > --- > .../bindings/memory-controllers/omap-gpmc.txt | 5 +- Acked-by: Rob Herring > drivers/memory/omap-gpmc.c | 106 +++++++++++++++++---- > 2 files changed, 92 insertions(+), 19 deletions(-) From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH v6 15/17] memory: omap-gpmc: Support WAIT pin edge interrupts Date: Mon, 11 Apr 2016 10:03:44 -0500 Message-ID: <20160411150344.GA3549@rob-hp-laptop> References: <1460023715-19332-1-git-send-email-rogerq@ti.com> <1460023715-19332-16-git-send-email-rogerq@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1460023715-19332-16-git-send-email-rogerq-l0cyMroinI0@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Roger Quadros Cc: tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org, computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org, ezequiel-30ULvvUtt6G51wMPkGsGjgyUoB5FGQPZ@public.gmane.org, javier-0uQlZySMnqxg9hUCZPvPmw@public.gmane.org, fcooper-l0cyMroinI0@public.gmane.org, nsekhar-l0cyMroinI0@public.gmane.org, linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On Thu, Apr 07, 2016 at 01:08:33PM +0300, Roger Quadros wrote: > OMAPs can have 2 to 4 WAITPINs that can be used as edge triggered > interrupts if not used for memory wait state insertion. > > Support these interrupts via the gpmc IRQ domain. > > The gpmc IRQ domain interrupt map is: > > 0 - NAND_fifoevent > 1 - NAND_termcount > 2 - GPMC_WAIT0 edge > 3 - GPMC_WAIT1 edge, and so on > > Signed-off-by: Roger Quadros > --- > .../bindings/memory-controllers/omap-gpmc.txt | 5 +- Acked-by: Rob Herring > drivers/memory/omap-gpmc.c | 106 +++++++++++++++++---- > 2 files changed, 92 insertions(+), 19 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html