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From: Chris Wilson <chris@chris-wilson.co.uk>
To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 3/3] drm/i915: Only grab correct forcewake for the engine with execlists
Date: Tue, 12 Apr 2016 14:18:27 +0100	[thread overview]
Message-ID: <20160412131827.GQ20240@nuc-i3427.alporthouse.com> (raw)
In-Reply-To: <1460044560-30582-1-git-send-email-tvrtko.ursulin@linux.intel.com>

On Thu, Apr 07, 2016 at 04:56:00PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Rather than blindly waking up all forcewake domains on command
> submission, we can teach each engine what is (or are) the correct
> one to take.
> 
> On platforms with multiple forcewake domains like VLV, CHV, SKL
> and BXT, this has the potential of lowering the GPU and CPU
> power use and submission latency.
> 
> To implement it we add a function named
> intel_uncore_forcewake_for_reg whose purpose is to query which
> forcewake domains need to be taken to read or write a specific
> register with raw mmio accessors.
> 
> These enables the execlists engine setup  to query which
> forcewake domains are relevant per engine on the currently
> running platform.
> 
> v2:
>   * Kerneldoc.
>   * Split from intel_uncore.c macro extraction, WARN_ON,
>     no warns on old platforms. (Chris Wilson)
> 
> v3:
>   * Single domain per engine, mention all registers,
>     bi-directional function and a new name, fix handling
>     of gen6 and gen7 writes. (Chris Wilson)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>

> +/**
> + * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
> + * 				    a register
> + * @dev_priv: pointer to struct drm_i915_private
> + * @reg: register in question
> + * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
> + *
> + * Returns a set of forcewake domains required to be taken with for example
> + * intel_uncore_forcewake_get for the specified register to be accessible in the
> + * specified mode (read, write or read/write) with raw mmio accessors.
> + *
> + * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
> + * callers to do FIFO management on their own or risk losing writes.
> + */
> +enum forcewake_domains
> +intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
> +			       i915_reg_t reg, unsigned int op)
> +{
> +	enum forcewake_domains fw_domains = 0;
> +
> +	WARN_ON(!op);
> +
> +	if (op & FW_REG_READ)
> +		fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
> +
> +	if (op & FW_REG_WRITE)
> +		fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);
> +
> +	return fw_domains;
> +}

Like it, like it a lot.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2016-04-12 13:18 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-07 14:05 [PATCH 1/3] drm/i915: Extract knowledge of register forcewake domains Tvrtko Ursulin
2016-04-07 14:05 ` [PATCH 2/3] drm/i915: Remove forcewake request registers from the shadowed table Tvrtko Ursulin
2016-04-07 14:41   ` Chris Wilson
2016-04-07 14:05 ` [PATCH 3/3] drm/i915: Only grab correct forcewake for the engine with execlists Tvrtko Ursulin
2016-04-07 14:24   ` Chris Wilson
2016-04-07 14:36     ` Tvrtko Ursulin
2016-04-07 14:59       ` Chris Wilson
2016-04-07 14:35   ` Chris Wilson
2016-04-07 14:52     ` Tvrtko Ursulin
2016-04-07 15:33       ` Chris Wilson
2016-04-07 15:56         ` [PATCH v3 " Tvrtko Ursulin
2016-04-12 13:18           ` Chris Wilson [this message]
2016-04-07 14:40 ` [PATCH 1/3] drm/i915: Extract knowledge of register forcewake domains Chris Wilson
2016-04-07 16:32 ` ✗ Fi.CI.BAT: failure for series starting with [1/3] " Patchwork

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