From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.fireflyinternet.com ([87.106.93.118]:63126 "EHLO fireflyinternet.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933499AbcDLPQX (ORCPT ); Tue, 12 Apr 2016 11:16:23 -0400 Date: Tue, 12 Apr 2016 16:16:04 +0100 From: Chris Wilson To: Mika Kuoppala Cc: =?utf-8?Q?Micha=C5=82?= Winiarski , intel-gfx@lists.freedesktop.org, stable@vger.kernel.org Subject: Re: [Intel-gfx] [PATCH v4] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write Message-ID: <20160412151604.GB21985@nuc-i3427.alporthouse.com> References: <1460469115-26002-1-git-send-email-michal.winiarski@intel.com> <87lh4jnd3k.fsf@gaia.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <87lh4jnd3k.fsf@gaia.fi.intel.com> Sender: stable-owner@vger.kernel.org List-ID: On Tue, Apr 12, 2016 at 04:58:07PM +0300, Mika Kuoppala wrote: > Michał Winiarski writes: > > > [ text/plain ] > > We started to use PIPE_CONTROL to write render ring seqno in order to > > combat seqno write vs interrupt generation problems. This was introduced > > by commit 7c17d377374d ("drm/i915: Use ordered seqno write interrupt > > generation on gen8+ execlists"). > > > > On gen8+ size of PIPE_CONTROL with Post Sync Operation should be > > 6 dwords. When we're using older 5-dword variant it's possible to > > observe inconsistent values written by PIPE_CONTROL with Post > > Sync Operation from user batches, resulting in rendering corruptions. > > > > v2: Fix BAT failures > > v3: Comments on alignment and thrashing high dword of seqno (Chris) > > v4: Updated commit msg (Mika) > > > > Testcase: igt/gem_pipe_control_store_loop/*-qword-write > > Issue: VIZ-7393 > > Cc: stable@vger.kernel.org > > Cc: Chris Wilson > > Cc: Mika Kuoppala > > Cc: Abdiel Janulgue > > Signed-off-by: Michał Winiarski > > Reviewed-by: Mika Kuoppala Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH v4] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write Date: Tue, 12 Apr 2016 16:16:04 +0100 Message-ID: <20160412151604.GB21985@nuc-i3427.alporthouse.com> References: <1460469115-26002-1-git-send-email-michal.winiarski@intel.com> <87lh4jnd3k.fsf@gaia.fi.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from fireflyinternet.com (mail.fireflyinternet.com [87.106.93.118]) by gabe.freedesktop.org (Postfix) with ESMTP id B939B6E05C for ; Tue, 12 Apr 2016 15:16:24 +0000 (UTC) Content-Disposition: inline In-Reply-To: <87lh4jnd3k.fsf@gaia.fi.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Mika Kuoppala Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org T24gVHVlLCBBcHIgMTIsIDIwMTYgYXQgMDQ6NTg6MDdQTSArMDMwMCwgTWlrYSBLdW9wcGFsYSB3 cm90ZToKPiBNaWNoYcWCIFdpbmlhcnNraSA8bWljaGFsLndpbmlhcnNraUBpbnRlbC5jb20+IHdy aXRlczoKPiAKPiA+IFsgdGV4dC9wbGFpbiBdCj4gPiBXZSBzdGFydGVkIHRvIHVzZSBQSVBFX0NP TlRST0wgdG8gd3JpdGUgcmVuZGVyIHJpbmcgc2Vxbm8gaW4gb3JkZXIgdG8KPiA+IGNvbWJhdCBz ZXFubyB3cml0ZSB2cyBpbnRlcnJ1cHQgZ2VuZXJhdGlvbiBwcm9ibGVtcy4gVGhpcyB3YXMgaW50 cm9kdWNlZAo+ID4gYnkgY29tbWl0IDdjMTdkMzc3Mzc0ZCAoImRybS9pOTE1OiBVc2Ugb3JkZXJl ZCBzZXFubyB3cml0ZSBpbnRlcnJ1cHQKPiA+IGdlbmVyYXRpb24gb24gZ2VuOCsgZXhlY2xpc3Rz IikuCj4gPgo+ID4gT24gZ2VuOCsgc2l6ZSBvZiBQSVBFX0NPTlRST0wgd2l0aCBQb3N0IFN5bmMg T3BlcmF0aW9uIHNob3VsZCBiZQo+ID4gNiBkd29yZHMuIFdoZW4gd2UncmUgdXNpbmcgb2xkZXIg NS1kd29yZCB2YXJpYW50IGl0J3MgcG9zc2libGUgdG8KPiA+IG9ic2VydmUgaW5jb25zaXN0ZW50 IHZhbHVlcyB3cml0dGVuIGJ5IFBJUEVfQ09OVFJPTCB3aXRoIFBvc3QKPiA+IFN5bmMgT3BlcmF0 aW9uIGZyb20gdXNlciBiYXRjaGVzLCByZXN1bHRpbmcgaW4gcmVuZGVyaW5nIGNvcnJ1cHRpb25z Lgo+ID4KPiA+IHYyOiBGaXggQkFUIGZhaWx1cmVzCj4gPiB2MzogQ29tbWVudHMgb24gYWxpZ25t ZW50IGFuZCB0aHJhc2hpbmcgaGlnaCBkd29yZCBvZiBzZXFubyAoQ2hyaXMpCj4gPiB2NDogVXBk YXRlZCBjb21taXQgbXNnIChNaWthKQo+ID4KPiA+IFRlc3RjYXNlOiBpZ3QvZ2VtX3BpcGVfY29u dHJvbF9zdG9yZV9sb29wLyotcXdvcmQtd3JpdGUKPiA+IElzc3VlOiBWSVotNzM5Mwo+ID4gQ2M6 IHN0YWJsZUB2Z2VyLmtlcm5lbC5vcmcKPiA+IENjOiBDaHJpcyBXaWxzb24gPGNocmlzQGNocmlz LXdpbHNvbi5jby51az4KPiA+IENjOiBNaWthIEt1b3BwYWxhIDxtaWthLmt1b3BwYWxhQGludGVs LmNvbT4KPiA+IENjOiBBYmRpZWwgSmFudWxndWUgPGFiZGllbC5qYW51bGd1ZUBsaW51eC5pbnRl bC5jb20+Cj4gPiBTaWduZWQtb2ZmLWJ5OiBNaWNoYcWCIFdpbmlhcnNraSA8bWljaGFsLndpbmlh cnNraUBpbnRlbC5jb20+Cj4gCj4gUmV2aWV3ZWQtYnk6IE1pa2EgS3VvcHBhbGEgPG1pa2Eua3Vv cHBhbGFAaW50ZWwuY29tPgpSZXZpZXdlZC1ieTogQ2hyaXMgV2lsc29uIDxjaHJpc0BjaHJpcy13 aWxzb24uY28udWs+Ci1DaHJpcwoKLS0gCkNocmlzIFdpbHNvbiwgSW50ZWwgT3BlbiBTb3VyY2Ug VGVjaG5vbG9neSBDZW50cmUKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0 b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50 ZWwtZ2Z4Cg==