From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966356AbcDMMQV (ORCPT ); Wed, 13 Apr 2016 08:16:21 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:1154 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965192AbcDMMQT (ORCPT ); Wed, 13 Apr 2016 08:16:19 -0400 Date: Wed, 13 Apr 2016 20:11:47 +0800 From: Jisheng Zhang To: Rob Herring CC: , , , , , , , , , , , Subject: Re: [PATCH] i2c: designware-platdrv: get fast/std speed scl high/low count from DT Message-ID: <20160413201147.5621a17c@xhacker> In-Reply-To: <20160407175759.GO32257@rob-hp-laptop> References: <1459927680-5480-1-git-send-email-jszhang@marvell.com> <20160407175759.GO32257@rob-hp-laptop> X-Mailer: Claws Mail 3.13.2 (GTK+ 2.24.30; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-04-13_05:,, signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1603180000 definitions=main-1604130177 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dear Rob, On Thu, 7 Apr 2016 12:57:59 -0500 Rob Herring wrote: > On Wed, Apr 06, 2016 at 03:28:00PM +0800, Jisheng Zhang wrote: > > Sometimes, it's convenient to define the scl's high/low count directly, > > e.g HW people would do some measurement then directly give out the > > optimum counts. Previously, we solved the sda falling time and scl > > falling time by i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt(), then put them > > into dt, but what we really care isn't the sda/scl falling time. > > This is just so you can put specific clock count instead of converting > from nanoseconds with standard properties or you gain some additional > control of the timing. If only the former, then I prefer we stick with > the common properties. To be honest, both. Let me show how I gain additional control of the timing with this patch while I can't do this w/o it. I want the similar high percent of SCL high for both standard-mode and fast-mode. Before this patch, this is not achievable because the parameters to cal the hcnt/lcnt via i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt() are different for standard-mode and fast-mode. Thanks, Jisheng > > > From another side, the dw_i2c_acpi_configure() on ACPI platform also > > get hcnt/lcnt values rather than the sda/scl falling time from ACPI > > method, we want similar feature for DT platforms. > > That's nice, but not really a reason IMO. > > > > > Signed-off-by: Jisheng Zhang > > --- > > Documentation/devicetree/bindings/i2c/i2c-designware.txt | 16 ++++++++++++++++ > > drivers/i2c/busses/i2c-designware-platdrv.c | 8 ++++++++ > > 2 files changed, 24 insertions(+) From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jisheng Zhang Subject: Re: [PATCH] i2c: designware-platdrv: get fast/std speed scl high/low count from DT Date: Wed, 13 Apr 2016 20:11:47 +0800 Message-ID: <20160413201147.5621a17c@xhacker> References: <1459927680-5480-1-git-send-email-jszhang@marvell.com> <20160407175759.GO32257@rob-hp-laptop> Mime-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20160407175759.GO32257@rob-hp-laptop> Sender: linux-i2c-owner@vger.kernel.org To: Rob Herring Cc: wsa@the-dreams.de, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, jarkko.nikula@linux.intel.com, andriy.shevchenko@linux.intel.com, mika.westerberg@linux.intel.com, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org Dear Rob, On Thu, 7 Apr 2016 12:57:59 -0500 Rob Herring wrote: > On Wed, Apr 06, 2016 at 03:28:00PM +0800, Jisheng Zhang wrote: > > Sometimes, it's convenient to define the scl's high/low count directly, > > e.g HW people would do some measurement then directly give out the > > optimum counts. Previously, we solved the sda falling time and scl > > falling time by i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt(), then put them > > into dt, but what we really care isn't the sda/scl falling time. > > This is just so you can put specific clock count instead of converting > from nanoseconds with standard properties or you gain some additional > control of the timing. If only the former, then I prefer we stick with > the common properties. To be honest, both. Let me show how I gain additional control of the timing with this patch while I can't do this w/o it. I want the similar high percent of SCL high for both standard-mode and fast-mode. Before this patch, this is not achievable because the parameters to cal the hcnt/lcnt via i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt() are different for standard-mode and fast-mode. Thanks, Jisheng > > > From another side, the dw_i2c_acpi_configure() on ACPI platform also > > get hcnt/lcnt values rather than the sda/scl falling time from ACPI > > method, we want similar feature for DT platforms. > > That's nice, but not really a reason IMO. > > > > > Signed-off-by: Jisheng Zhang > > --- > > Documentation/devicetree/bindings/i2c/i2c-designware.txt | 16 ++++++++++++++++ > > drivers/i2c/busses/i2c-designware-platdrv.c | 8 ++++++++ > > 2 files changed, 24 insertions(+) From mboxrd@z Thu Jan 1 00:00:00 1970 From: jszhang@marvell.com (Jisheng Zhang) Date: Wed, 13 Apr 2016 20:11:47 +0800 Subject: [PATCH] i2c: designware-platdrv: get fast/std speed scl high/low count from DT In-Reply-To: <20160407175759.GO32257@rob-hp-laptop> References: <1459927680-5480-1-git-send-email-jszhang@marvell.com> <20160407175759.GO32257@rob-hp-laptop> Message-ID: <20160413201147.5621a17c@xhacker> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Dear Rob, On Thu, 7 Apr 2016 12:57:59 -0500 Rob Herring wrote: > On Wed, Apr 06, 2016 at 03:28:00PM +0800, Jisheng Zhang wrote: > > Sometimes, it's convenient to define the scl's high/low count directly, > > e.g HW people would do some measurement then directly give out the > > optimum counts. Previously, we solved the sda falling time and scl > > falling time by i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt(), then put them > > into dt, but what we really care isn't the sda/scl falling time. > > This is just so you can put specific clock count instead of converting > from nanoseconds with standard properties or you gain some additional > control of the timing. If only the former, then I prefer we stick with > the common properties. To be honest, both. Let me show how I gain additional control of the timing with this patch while I can't do this w/o it. I want the similar high percent of SCL high for both standard-mode and fast-mode. Before this patch, this is not achievable because the parameters to cal the hcnt/lcnt via i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt() are different for standard-mode and fast-mode. Thanks, Jisheng > > > From another side, the dw_i2c_acpi_configure() on ACPI platform also > > get hcnt/lcnt values rather than the sda/scl falling time from ACPI > > method, we want similar feature for DT platforms. > > That's nice, but not really a reason IMO. > > > > > Signed-off-by: Jisheng Zhang > > --- > > Documentation/devicetree/bindings/i2c/i2c-designware.txt | 16 ++++++++++++++++ > > drivers/i2c/busses/i2c-designware-platdrv.c | 8 ++++++++ > > 2 files changed, 24 insertions(+)