From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38109) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aqXJ6-0002kR-8j for qemu-devel@nongnu.org; Wed, 13 Apr 2016 22:47:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aqXJ2-0000Vy-VV for qemu-devel@nongnu.org; Wed, 13 Apr 2016 22:47:00 -0400 Received: from mx1.redhat.com ([209.132.183.28]:60405) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aqXJ2-0000Vq-QV for qemu-devel@nongnu.org; Wed, 13 Apr 2016 22:46:56 -0400 Date: Thu, 14 Apr 2016 10:46:45 +0800 From: Peter Xu Message-ID: <20160414024645.GB25961@pxdev.xzpeter.org> References: <1460366363-4589-1-git-send-email-peterx@redhat.com> <1460366363-4589-13-git-send-email-peterx@redhat.com> <570C860A.4060203@web.de> <20160412090239.GA17558@pxdev.xzpeter.org> <570D1696.2080301@web.de> <20160413033304.GB17558@pxdev.xzpeter.org> <570DBF69.2030302@web.de> <20160413100643.GG17558@pxdev.xzpeter.org> <570E5B66.9000700@web.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <570E5B66.9000700@web.de> Subject: Re: [Qemu-devel] [PATCH v2 12/13] intel_iommu: ioapic: IR support for emulated IOAPIC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jan Kiszka Cc: qemu-devel@nongnu.org, imammedo@redhat.com, rth@twiddle.net, ehabkost@redhat.com, jasowang@redhat.com, marcel@redhat.com, mst@redhat.com, pbonzini@redhat.com, rkrcmar@redhat.com On Wed, Apr 13, 2016 at 07:44:54AM -0700, Jan Kiszka wrote: [...] > > One thing I am curious about: I see that in vtd spec 5.1.5.1: > > > > "RTE bits 10:8 is programmed to 000b (Fixed) to force the SHV > > (SubHandle Valid) field as Clear in the interrupt address > > generated." > > > > So... In real IOMMU hardwares, IOAPIC interrupt will finally be > > translated to MSI as well? am I understanding it correctly? > > It will be translated into something that the IR unit can receive - > whatever that is technically. Logically, there is no difference to MSIs > received from PCI devices. Ok. I see there are still differences between IOAPIC and MSI, e.g., for IOAPIC entries, it has "Interrupt Input Pin Polarity", which is bit 13 of the entry, to show whether 1 or 0 is taken as assertion for level-triggered interrupts. While in MSI, I assume assertion will be 1 always. Can I take it as "obsolete" and we will never use it? If to take IOAPIC entries as MSI messages, all these extra bits will be dropped (it's dropped in ioapic_service() already, but not sure whether we will pick them up in the future). > > > > > Btw, if to use the way you suggested, the patch content would > > possibly be very alike the one you and Rita has posted, which is: > > > > https://lists.gnu.org/archive/html/qemu-devel/2016-03/msg01933.html > > > > I will only pick up those lines I needed in supporting IOAPIC. If > > so, do you mind I add your s-o-b as well above mine (maybe add > > Rita's too)? > > If a patch is almost identical, add your [Peter: my changes...] line and > your signed of to it. If it is more modified, claim authorship and just > refer to the original authors in the commit log. Ok. Thanks. -- peterx