From: Chris Wilson <chris@chris-wilson.co.uk>
To: ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 05/12] drm/i915: Clear VLV_IER around irq processing
Date: Thu, 14 Apr 2016 10:36:00 +0100 [thread overview]
Message-ID: <20160414093600.GF5683@nuc-i3427.alporthouse.com> (raw)
In-Reply-To: <1460571598-24452-6-git-send-email-ville.syrjala@linux.intel.com>
On Wed, Apr 13, 2016 at 09:19:51PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On VLV/CHV the master interrupt enable bit only affects GT/PM
> interrupts. Display interrupts are not affected by the master
> irq control.
>
> Also it seems that the CPU interrupt will only be generated when
> the combined result of all GT/PM/display interrupts has a 0->1
> edge. We already use the master interrupt enable bit to make sure
> GT/PM interrupt can generate such an edge if we don't end up clearing
> all IIR bits. We must do the same for display interrupts, and for
> that we can simply clear out VLV_IER, and restore after we've acked
> all the interrupts we are about to process.
>
> So with both master interrupt enable and VLV_IER cleared out, we will
> guarantee that there will be a 0->1 edge if any IIR bits are still set
> at the end, and thus another CPU interrupt will be generated.
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Fixes: 579de73b048a ("drm/i915: Exit cherryview_irq_handler() after one pass")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Ville is very persuasive,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Other than wishing the extra POSTING_READ and reading known registers
away, the rest of the series is also
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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next prev parent reply other threads:[~2016-04-14 9:36 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-13 18:19 [PATCH 00/12] drm/i915: VLV/CHV irq handler fixes ville.syrjala
2016-04-13 18:19 ` [PATCH 01/12] drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistently ville.syrjala
2016-04-13 18:19 ` [PATCH 02/12] drm/i915: Set up VLV_MASTER_IER consistently ville.syrjala
2016-04-13 18:19 ` [PATCH 03/12] drm/i915: Clear VLV_IIR after PIPESTAT ville.syrjala
2016-04-13 18:19 ` [PATCH 04/12] drm/i915: Clear VLV_MASTER_IER around irq processing ville.syrjala
2016-04-13 18:19 ` [PATCH 05/12] drm/i915: Clear VLV_IER " ville.syrjala
2016-04-13 20:53 ` Chris Wilson
2016-04-14 8:22 ` Ville Syrjälä
2016-04-14 8:32 ` Chris Wilson
2016-04-14 8:49 ` Ville Syrjälä
2016-04-14 9:36 ` Chris Wilson [this message]
2016-04-14 12:30 ` Ville Syrjälä
2016-04-14 12:47 ` Mika Kuoppala
2016-04-15 7:32 ` Mika Kuoppala
2016-04-13 18:19 ` [PATCH 06/12] drm/i915: Eliminate loop from VLV irq handler ville.syrjala
2016-04-13 18:19 ` [PATCH 07/12] drm/i915: Move variables to narrower scope in VLV/CHV irq handlers ville.syrjala
2016-04-13 18:19 ` [PATCH 08/12] drm/i915: Split PORT_HOTPLUG_STAT ack out from i9xx_hpd_irq_handler() ville.syrjala
2016-04-13 18:19 ` [PATCH 09/12] drm/i915: Split VLV/CVH PIPESTAT handling into ack+handler ville.syrjala
2016-04-13 18:19 ` [PATCH 10/12] drm/i915: Move gt/pm irq handling out from irq disabled section on VLV ville.syrjala
2016-04-13 18:19 ` [PATCH 11/12] drm/i915: Eliminate passing dev+dev_priv to {snb, ilk}_gt_irq_handler() ville.syrjala
2016-04-13 21:02 ` Daniel Vetter
2016-04-13 18:19 ` [PATCH 12/12] drm/i915: Split gen8_gt_irq_handler into ack+handle ville.syrjala
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