From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753438AbcDURsg (ORCPT ); Thu, 21 Apr 2016 13:48:36 -0400 Received: from mail.skyhub.de ([78.46.96.112]:37890 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751871AbcDURsf (ORCPT ); Thu, 21 Apr 2016 13:48:35 -0400 Date: Thu, 21 Apr 2016 19:48:13 +0200 From: Borislav Petkov To: Alexander Shishkin Cc: Peter Zijlstra , Ingo Molnar , linux-kernel@vger.kernel.org, vince@deater.net, eranian@google.com, Arnaldo Carvalho de Melo , Mathieu Poirier Subject: Re: [PATCH v1 2/5] perf/x86/intel/pt: IP filtering register/cpuid bits Message-ID: <20160421174813.GA29639@pd.tnic> References: <1461251823-12416-1-git-send-email-alexander.shishkin@linux.intel.com> <1461251823-12416-3-git-send-email-alexander.shishkin@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1461251823-12416-3-git-send-email-alexander.shishkin@linux.intel.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 21, 2016 at 06:17:00PM +0300, Alexander Shishkin wrote: > New versions of Intel PT support address range-based filtering. These > are the registers, bit definitions and relevant CPUID bits. > > Signed-off-by: Alexander Shishkin > --- > arch/x86/events/intel/pt.c | 2 ++ > arch/x86/events/intel/pt.h | 2 ++ > arch/x86/include/asm/msr-index.h | 18 ++++++++++++++++++ > 3 files changed, 22 insertions(+) > > diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c > index 127f58c179..891447dd61 100644 > --- a/arch/x86/events/intel/pt.c > +++ b/arch/x86/events/intel/pt.c > @@ -67,11 +67,13 @@ static struct pt_cap_desc { > PT_CAP(max_subleaf, 0, CR_EAX, 0xffffffff), > PT_CAP(cr3_filtering, 0, CR_EBX, BIT(0)), > PT_CAP(psb_cyc, 0, CR_EBX, BIT(1)), > + PT_CAP(ip_filtering, 0, CR_EBX, BIT(2)), > PT_CAP(mtc, 0, CR_EBX, BIT(3)), > PT_CAP(topa_output, 0, CR_ECX, BIT(0)), > PT_CAP(topa_multiple_entries, 0, CR_ECX, BIT(1)), > PT_CAP(single_range_output, 0, CR_ECX, BIT(2)), > PT_CAP(payloads_lip, 0, CR_ECX, BIT(31)), > + PT_CAP(num_address_ranges, 1, CR_EAX, 0x3), > PT_CAP(mtc_periods, 1, CR_EAX, 0xffff0000), > PT_CAP(cycle_thresholds, 1, CR_EBX, 0xffff), > PT_CAP(psb_periods, 1, CR_EBX, 0xffff0000), > diff --git a/arch/x86/events/intel/pt.h b/arch/x86/events/intel/pt.h > index 336878a5d2..6ce8cd20b9 100644 > --- a/arch/x86/events/intel/pt.h > +++ b/arch/x86/events/intel/pt.h > @@ -52,11 +52,13 @@ enum pt_capabilities { > PT_CAP_max_subleaf = 0, > PT_CAP_cr3_filtering, > PT_CAP_psb_cyc, > + PT_CAP_ip_filtering, > PT_CAP_mtc, > PT_CAP_topa_output, > PT_CAP_topa_multiple_entries, > PT_CAP_single_range_output, > PT_CAP_payloads_lip, > + PT_CAP_num_address_ranges, > PT_CAP_mtc_periods, > PT_CAP_cycle_thresholds, > PT_CAP_psb_periods, > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index e0e2f7dfbd..964d7e17a6 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -105,11 +105,29 @@ > #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) > #define RTIT_CTL_PSB_FREQ_OFFSET 24 > #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) > +#define RTIT_CTL_ADDR0_OFFSET 32 > +#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) > +#define RTIT_CTL_ADDR1_OFFSET 36 > +#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) > +#define RTIT_CTL_ADDR2_OFFSET 40 > +#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) > +#define RTIT_CTL_ADDR3_OFFSET 44 > +#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) > #define MSR_IA32_RTIT_STATUS 0x00000571 > +#define RTIT_STATUS_FILTEREN BIT(0) > #define RTIT_STATUS_CONTEXTEN BIT(1) > #define RTIT_STATUS_TRIGGEREN BIT(2) > +#define RTIT_STATUS_BUFFOVF BIT(3) > #define RTIT_STATUS_ERROR BIT(4) > #define RTIT_STATUS_STOPPED BIT(5) > +#define MSR_IA32_RTIT_ADDR0_A 0x00000580 > +#define MSR_IA32_RTIT_ADDR0_B 0x00000581 > +#define MSR_IA32_RTIT_ADDR1_A 0x00000582 > +#define MSR_IA32_RTIT_ADDR1_B 0x00000583 > +#define MSR_IA32_RTIT_ADDR2_A 0x00000584 > +#define MSR_IA32_RTIT_ADDR2_B 0x00000585 > +#define MSR_IA32_RTIT_ADDR3_A 0x00000586 > +#define MSR_IA32_RTIT_ADDR3_B 0x00000587 So can we not turn msr-index.h a dumping ground for MSRs pls? If those are only PT-relevant, why not define them all in pt.h? -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply.