From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753265AbcDXUjg (ORCPT ); Sun, 24 Apr 2016 16:39:36 -0400 Received: from sauhun.de ([89.238.76.85]:40873 "EHLO pokefinder.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753124AbcDXUje (ORCPT ); Sun, 24 Apr 2016 16:39:34 -0400 Date: Sun, 24 Apr 2016 22:39:23 +0200 From: Wolfram Sang To: Jisheng Zhang Cc: Rob Herring , pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, jarkko.nikula@linux.intel.com, andriy.shevchenko@linux.intel.com, mika.westerberg@linux.intel.com, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] i2c: designware-platdrv: get fast/std speed scl high/low count from DT Message-ID: <20160424203922.GC4317@katana> References: <1459927680-5480-1-git-send-email-jszhang@marvell.com> <20160407175759.GO32257@rob-hp-laptop> <20160413201147.5621a17c@xhacker> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="DIOMP1UsTsWJauNi" Content-Disposition: inline In-Reply-To: <20160413201147.5621a17c@xhacker> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --DIOMP1UsTsWJauNi Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Apr 13, 2016 at 08:11:47PM +0800, Jisheng Zhang wrote: > Dear Rob, >=20 > On Thu, 7 Apr 2016 12:57:59 -0500 Rob Herring wrote: >=20 > > On Wed, Apr 06, 2016 at 03:28:00PM +0800, Jisheng Zhang wrote: > > > Sometimes, it's convenient to define the scl's high/low count directl= y, > > > e.g HW people would do some measurement then directly give out the > > > optimum counts. Previously, we solved the sda falling time and scl > > > falling time by i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt(), then put them > > > into dt, but what we really care isn't the sda/scl falling time. =20 > >=20 > > This is just so you can put specific clock count instead of converting= =20 > > from nanoseconds with standard properties or you gain some additional= =20 > > control of the timing. If only the former, then I prefer we stick with= =20 > > the common properties. >=20 > To be honest, both. Let me show how I gain additional control of the timi= ng > with this patch while I can't do this w/o it. >=20 > I want the similar high percent of SCL high for both standard-mode and > fast-mode. Before this patch, this is not achievable because the paramete= rs > to cal the hcnt/lcnt via i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt() are diff= erent > for standard-mode and fast-mode. If there is something you can't describe currently, then we can add additional properties to allow you to do what you want. But they should be generic bindings and not a plain value which is custom to this driver. --DIOMP1UsTsWJauNi Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJXHS76AAoJEBQN5MwUoCm2C78P/R8ahfoIxSpEMtC6XHd1LXmc ZB/TXqtB2llMLRR0umlTwgzticDSWLWXQ3LkWLI/XnofxYhiRquakpIqEuIfsqME DAo3Vdr1TrLHIVmZFMDQEZO3Wj/yzEQIpJf+uWkcjzIulQbHLfLybagfJX1JNNnb sxM++07ybQ37QkXb3Yj7YxU1iUmTKa26JPWAl6uBXjLwCvlIz2o26LFyDxuclaOe J5z3ij5m2EQeNjlZ/MzXf4fGBsdlHcs7A+qomuB1P7P8POZ8fqivhH6+gaBG1P/J jtrpcolECKfJM8K+3RE3XFPTlhPCQRuMHLu0xe0WlpG8AZxoV+N+cobx+rQNLa4E X86AK5poUkV7l5UI49nQ6Z18WLYoh+KT+EQdYutw5y59KiCPx+N7FBI7bGQ9sojW v9uhuzPLaT3xpL6rvwZhPIenb2n025bFRVoabDkZQZqB1siBPrTA1wbHX/cALwG5 V4mykeBQvGJbsggW3Aio1x7bX8SUdzkG5AtBKguh2ZGM37kWWghPhjDfNDeFV+Wn pYLw21W8IRBEvdzUczEUwTSqL+KwxxhNhwGTz99+ERvFytQrMi8wtUJ/0FoUd5XC jW4Fvh8S1PGtgD/v9I2VAS+oz4xzt/XcJpZahJ3sumf2sxPLVsFZaY6PcWvlKkD2 +wYm1hciZn+E/lPrl97P =z6p2 -----END PGP SIGNATURE----- --DIOMP1UsTsWJauNi-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wolfram Sang Subject: Re: [PATCH] i2c: designware-platdrv: get fast/std speed scl high/low count from DT Date: Sun, 24 Apr 2016 22:39:23 +0200 Message-ID: <20160424203922.GC4317@katana> References: <1459927680-5480-1-git-send-email-jszhang@marvell.com> <20160407175759.GO32257@rob-hp-laptop> <20160413201147.5621a17c@xhacker> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="DIOMP1UsTsWJauNi" Return-path: Content-Disposition: inline In-Reply-To: <20160413201147.5621a17c@xhacker> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Jisheng Zhang Cc: Rob Herring , pawel.moll-5wv7dgnIgG8@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, jarkko.nikula-VuQAYsv1563Yd54FQh9/CA@public.gmane.org, andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org, mika.westerberg-VuQAYsv1563Yd54FQh9/CA@public.gmane.org, linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org --DIOMP1UsTsWJauNi Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Apr 13, 2016 at 08:11:47PM +0800, Jisheng Zhang wrote: > Dear Rob, >=20 > On Thu, 7 Apr 2016 12:57:59 -0500 Rob Herring wrote: >=20 > > On Wed, Apr 06, 2016 at 03:28:00PM +0800, Jisheng Zhang wrote: > > > Sometimes, it's convenient to define the scl's high/low count directl= y, > > > e.g HW people would do some measurement then directly give out the > > > optimum counts. Previously, we solved the sda falling time and scl > > > falling time by i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt(), then put them > > > into dt, but what we really care isn't the sda/scl falling time. =20 > >=20 > > This is just so you can put specific clock count instead of converting= =20 > > from nanoseconds with standard properties or you gain some additional= =20 > > control of the timing. If only the former, then I prefer we stick with= =20 > > the common properties. >=20 > To be honest, both. Let me show how I gain additional control of the timi= ng > with this patch while I can't do this w/o it. >=20 > I want the similar high percent of SCL high for both standard-mode and > fast-mode. Before this patch, this is not achievable because the paramete= rs > to cal the hcnt/lcnt via i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt() are diff= erent > for standard-mode and fast-mode. If there is something you can't describe currently, then we can add additional properties to allow you to do what you want. But they should be generic bindings and not a plain value which is custom to this driver. --DIOMP1UsTsWJauNi Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJXHS76AAoJEBQN5MwUoCm2C78P/R8ahfoIxSpEMtC6XHd1LXmc ZB/TXqtB2llMLRR0umlTwgzticDSWLWXQ3LkWLI/XnofxYhiRquakpIqEuIfsqME DAo3Vdr1TrLHIVmZFMDQEZO3Wj/yzEQIpJf+uWkcjzIulQbHLfLybagfJX1JNNnb sxM++07ybQ37QkXb3Yj7YxU1iUmTKa26JPWAl6uBXjLwCvlIz2o26LFyDxuclaOe J5z3ij5m2EQeNjlZ/MzXf4fGBsdlHcs7A+qomuB1P7P8POZ8fqivhH6+gaBG1P/J jtrpcolECKfJM8K+3RE3XFPTlhPCQRuMHLu0xe0WlpG8AZxoV+N+cobx+rQNLa4E X86AK5poUkV7l5UI49nQ6Z18WLYoh+KT+EQdYutw5y59KiCPx+N7FBI7bGQ9sojW v9uhuzPLaT3xpL6rvwZhPIenb2n025bFRVoabDkZQZqB1siBPrTA1wbHX/cALwG5 V4mykeBQvGJbsggW3Aio1x7bX8SUdzkG5AtBKguh2ZGM37kWWghPhjDfNDeFV+Wn pYLw21W8IRBEvdzUczEUwTSqL+KwxxhNhwGTz99+ERvFytQrMi8wtUJ/0FoUd5XC jW4Fvh8S1PGtgD/v9I2VAS+oz4xzt/XcJpZahJ3sumf2sxPLVsFZaY6PcWvlKkD2 +wYm1hciZn+E/lPrl97P =z6p2 -----END PGP SIGNATURE----- --DIOMP1UsTsWJauNi-- -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: wsa@the-dreams.de (Wolfram Sang) Date: Sun, 24 Apr 2016 22:39:23 +0200 Subject: [PATCH] i2c: designware-platdrv: get fast/std speed scl high/low count from DT In-Reply-To: <20160413201147.5621a17c@xhacker> References: <1459927680-5480-1-git-send-email-jszhang@marvell.com> <20160407175759.GO32257@rob-hp-laptop> <20160413201147.5621a17c@xhacker> Message-ID: <20160424203922.GC4317@katana> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Apr 13, 2016 at 08:11:47PM +0800, Jisheng Zhang wrote: > Dear Rob, > > On Thu, 7 Apr 2016 12:57:59 -0500 Rob Herring wrote: > > > On Wed, Apr 06, 2016 at 03:28:00PM +0800, Jisheng Zhang wrote: > > > Sometimes, it's convenient to define the scl's high/low count directly, > > > e.g HW people would do some measurement then directly give out the > > > optimum counts. Previously, we solved the sda falling time and scl > > > falling time by i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt(), then put them > > > into dt, but what we really care isn't the sda/scl falling time. > > > > This is just so you can put specific clock count instead of converting > > from nanoseconds with standard properties or you gain some additional > > control of the timing. If only the former, then I prefer we stick with > > the common properties. > > To be honest, both. Let me show how I gain additional control of the timing > with this patch while I can't do this w/o it. > > I want the similar high percent of SCL high for both standard-mode and > fast-mode. Before this patch, this is not achievable because the parameters > to cal the hcnt/lcnt via i2c_dw_scl_hcnt() and i2c_dw_scl_lcnt() are different > for standard-mode and fast-mode. If there is something you can't describe currently, then we can add additional properties to allow you to do what you want. But they should be generic bindings and not a plain value which is custom to this driver. -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: