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From: Chris Wilson <chris@chris-wilson.co.uk>
To: Eero Tamminen <eero.t.tamminen@intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Frederick, Michael T" <michael.t.frederick@intel.com>,
	"Rantala, Valtteri" <valtteri.rantala@intel.com>
Subject: Re: [PATCH v2 2/2] drm/i915/bxt: Fix inadvertent CPU snooping due to incorrect MOCS config
Date: Wed, 27 Apr 2016 15:53:04 +0100	[thread overview]
Message-ID: <20160427145304.GG27856@nuc-i3427.alporthouse.com> (raw)
In-Reply-To: <5720BDB5.2050600@intel.com>

On Wed, Apr 27, 2016 at 04:25:09PM +0300, Eero Tamminen wrote:
> Hi,
> 
> On 26.04.2016 20:25, Frederick, Michael T wrote:
> >Sorry I'm not tracking all the MOCs discussions.  I just want to indicate what the coherency means in SoC for BXT.
> >
> >GTI sets the non-inclusive bit on the IDI interface based on how it treats the memory.  In BXT case where there is no uncore cache, "non-inclusive" just indicates snoop or not.  BXT has a snoop filter in order to make the latency of snooping GT from a core roughly similar to snooping another core.
> >
> >For BXT:
> >If GTI sets non-inclusive=0 (i.e. coherent): transaction looks up in the SF and the SA snoops the cores.  The potential impact here is that for high BW coherent traffic, the SF will become the BW limiter of the system and cap BW at 33% * 34GBps. For writes like WCILFs snoops to cores must be resolved before SA requests WR data from GT.  For reads the common case should have no impact because snoop latency is generally much less than memory data latency.  In general snoop latency for a core is relatively small, but there is also the prospect that a core could be down (e.g. ratio change) or loaded w/ snooping.
> >If GTI sets non-inclusive=1 (i.e. non-coherent): transaction takes the SF bypass and the SA does not snoop the cores.  This is best for high-BW since it removes the SF bottleneck and doesn't require core interaction.
> 
> Thanks for the explanation!
> 
> AFAIK:
> 
> * In regards to 3D driver operations, CPU side doesn't modify the
> buffer contents while GPU is working on them.  CPU side sets up the
> buffers (textures, VBOs, batches etc), and then (after a flush) GPU
> is asked to act on them.
> 
> * For things like texture streaming, the driver either internally
> synchronizes the data or creates a new copy of it whenever
> application tells that data is updated.  There's always some kind of
> "upload" involved (GL API needs it as non-integrated GPU's don't
> share memory with CPU).
> 
> While it's possible that there's a case where snooping would be
> needed, I cannot think of any myself.
> 
> Daniel, Chris, did you have some concrete example in mind where 3D
> driver would require CPU to snoop GPU?

Not mesa, but X can do concurrent rendering to a Pixmap whilst also
rendering from other parts of that Pixmap into a GPU side buffer and
presentation/compositing thereof. X uses snooping both ways (from client
memory to GPU and from GPU to client memory) as well as mixed rendering.

Mesa should be using snooping for both SubTexImage and GetTexImage. On
the SubTexImage path you can use the sampler to do format conversions
that even including the sync overhead for correctness when using client
memory avoid the awful format conversion code in mesa. Using the GPU to
write into client memory and avoiding WC reads is approximately an
order of magnitude (8x) faster than the current code mesa uses.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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  reply	other threads:[~2016-04-27 14:53 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-26 12:44 [PATCH v2 1/2] drm/i915/gen9: Clean up MOCS table definitions Imre Deak
2016-04-26 12:44 ` [PATCH v2 2/2] drm/i915/bxt: Fix inadvertent CPU snooping due to incorrect MOCS config Imre Deak
2016-04-26 12:57   ` Chris Wilson
2016-04-26 13:17     ` Imre Deak
2016-04-26 13:23       ` Chris Wilson
2016-04-26 13:43         ` Imre Deak
2016-04-26 13:58           ` Chris Wilson
2016-04-26 14:26         ` Eero Tamminen
2016-04-26 14:30           ` Daniel Vetter
2016-04-26 17:18             ` Eero Tamminen
2016-04-26 17:25               ` Frederick, Michael T
2016-04-27 13:25                 ` Eero Tamminen
2016-04-27 14:53                   ` Chris Wilson [this message]
2016-04-27 18:42                     ` Dave Gordon
2016-04-29  8:01                     ` Eero Tamminen
2016-04-26 17:57             ` Ville Syrjälä
2016-04-28  8:13               ` Daniel Vetter
2016-04-28 10:48                 ` Ville Syrjälä
2016-04-28 14:44                   ` Daniel Vetter
2016-04-28 17:21                     ` Ville Syrjälä
2016-04-26 14:42           ` Chris Wilson
2016-04-26 16:01             ` Imre Deak
2016-04-28  8:17               ` Daniel Vetter
2016-04-28  8:38                 ` Imre Deak
2016-04-28 14:48                   ` Daniel Vetter
2016-04-28 17:15                     ` Imre Deak
2016-05-02  8:28                       ` Daniel Vetter
2016-05-02 11:18                         ` Ville Syrjälä
2016-05-02 13:50                         ` Imre Deak
2016-04-28 17:25                     ` Ville Syrjälä
2016-04-26 13:12   ` Chris Wilson
2016-04-26 16:55 ` ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/gen9: Clean up MOCS table definitions Patchwork

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