From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753427AbcD0RRG (ORCPT ); Wed, 27 Apr 2016 13:17:06 -0400 Received: from muru.com ([72.249.23.125]:52481 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752517AbcD0RRD (ORCPT ); Wed, 27 Apr 2016 13:17:03 -0400 Date: Wed, 27 Apr 2016 10:16:58 -0700 From: Tony Lindgren To: Tero Kristo Cc: "J.D. Schroeder" , linux-kernel@vger.kernel.org, bcousson@baylibre.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "J.D. Schroeder" Subject: Re: [PATCH 1/3] DRA7: Fix clock data for gmac_gmii_ref_clk_div Message-ID: <20160427171658.GA5995@atomide.com> References: <1461693269-19436-1-git-send-email-Linux.HWI@garmin.com> <1461693269-19436-2-git-send-email-Linux.HWI@garmin.com> <5720A09F.2060701@ti.com> <20160427163640.GZ5995@atomide.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160427163640.GZ5995@atomide.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Tony Lindgren [160427 09:39]: > * Tero Kristo [160427 04:22]: > > On 26/04/16 20:54, J.D. Schroeder wrote: > > >From: "J.D. Schroeder" > > > > > >This commit fixes the clock data inside the DRA7xx clocks device tree > > >structure for the gmac_gmii_ref_clk_div clock. This clock is actually > > >the GMAC_MAIN_CLK and has nothing to do with the register at address > > >0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is > > >set to 1 in order to use the GMAC_RMII_CLK instead of the > > >GMAC_RMII_HS_CLK, the kernel generates a clock divider warning: > > > WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0() > > > gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set > > > > > >By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to > > >have the parent of dpll_gmac_m2_ck always divided by 2 the warning is > > >resolved and the clock tree is fixed up. > > > > > >Additionally, a new clock called rmii_50mhz_clk_mux is defined that > > >does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the > > >source clock for the RMII_50MHZ_CLK. > > > > > >Signed-off-by: J.D. Schroeder > > >Reviewed-by: Trenton Andres > > > > Looks like something weird happened with the clock data conversion tool with > > this specific clock. Seems to be the only buggy instance in our clock data > > across SoCs. Good catch. > > > > Acked-by: Tero Kristo > > Applying into omap-for-v4.6/fixes thanks. Actually then we end up creating self-inflicted merge conflict here with next. So let's wait a bit on this one as it's harmless. J.D. can you please rebase this against current Linux next? Note the recent unit name and unit address fixes for warnings with make W=1 dtbs. Regards, Tony From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tony Lindgren Subject: Re: [PATCH 1/3] DRA7: Fix clock data for gmac_gmii_ref_clk_div Date: Wed, 27 Apr 2016 10:16:58 -0700 Message-ID: <20160427171658.GA5995@atomide.com> References: <1461693269-19436-1-git-send-email-Linux.HWI@garmin.com> <1461693269-19436-2-git-send-email-Linux.HWI@garmin.com> <5720A09F.2060701@ti.com> <20160427163640.GZ5995@atomide.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20160427163640.GZ5995-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Tero Kristo Cc: "J.D. Schroeder" , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, bcousson-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, "J.D. Schroeder" List-Id: devicetree@vger.kernel.org * Tony Lindgren [160427 09:39]: > * Tero Kristo [160427 04:22]: > > On 26/04/16 20:54, J.D. Schroeder wrote: > > >From: "J.D. Schroeder" > > > > > >This commit fixes the clock data inside the DRA7xx clocks device tree > > >structure for the gmac_gmii_ref_clk_div clock. This clock is actually > > >the GMAC_MAIN_CLK and has nothing to do with the register at address > > >0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is > > >set to 1 in order to use the GMAC_RMII_CLK instead of the > > >GMAC_RMII_HS_CLK, the kernel generates a clock divider warning: > > > WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0() > > > gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set > > > > > >By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to > > >have the parent of dpll_gmac_m2_ck always divided by 2 the warning is > > >resolved and the clock tree is fixed up. > > > > > >Additionally, a new clock called rmii_50mhz_clk_mux is defined that > > >does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the > > >source clock for the RMII_50MHZ_CLK. > > > > > >Signed-off-by: J.D. Schroeder > > >Reviewed-by: Trenton Andres > > > > Looks like something weird happened with the clock data conversion tool with > > this specific clock. Seems to be the only buggy instance in our clock data > > across SoCs. Good catch. > > > > Acked-by: Tero Kristo > > Applying into omap-for-v4.6/fixes thanks. Actually then we end up creating self-inflicted merge conflict here with next. So let's wait a bit on this one as it's harmless. J.D. can you please rebase this against current Linux next? Note the recent unit name and unit address fixes for warnings with make W=1 dtbs. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: tony@atomide.com (Tony Lindgren) Date: Wed, 27 Apr 2016 10:16:58 -0700 Subject: [PATCH 1/3] DRA7: Fix clock data for gmac_gmii_ref_clk_div In-Reply-To: <20160427163640.GZ5995@atomide.com> References: <1461693269-19436-1-git-send-email-Linux.HWI@garmin.com> <1461693269-19436-2-git-send-email-Linux.HWI@garmin.com> <5720A09F.2060701@ti.com> <20160427163640.GZ5995@atomide.com> Message-ID: <20160427171658.GA5995@atomide.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org * Tony Lindgren [160427 09:39]: > * Tero Kristo [160427 04:22]: > > On 26/04/16 20:54, J.D. Schroeder wrote: > > >From: "J.D. Schroeder" > > > > > >This commit fixes the clock data inside the DRA7xx clocks device tree > > >structure for the gmac_gmii_ref_clk_div clock. This clock is actually > > >the GMAC_MAIN_CLK and has nothing to do with the register at address > > >0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is > > >set to 1 in order to use the GMAC_RMII_CLK instead of the > > >GMAC_RMII_HS_CLK, the kernel generates a clock divider warning: > > > WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0() > > > gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set > > > > > >By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to > > >have the parent of dpll_gmac_m2_ck always divided by 2 the warning is > > >resolved and the clock tree is fixed up. > > > > > >Additionally, a new clock called rmii_50mhz_clk_mux is defined that > > >does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the > > >source clock for the RMII_50MHZ_CLK. > > > > > >Signed-off-by: J.D. Schroeder > > >Reviewed-by: Trenton Andres > > > > Looks like something weird happened with the clock data conversion tool with > > this specific clock. Seems to be the only buggy instance in our clock data > > across SoCs. Good catch. > > > > Acked-by: Tero Kristo > > Applying into omap-for-v4.6/fixes thanks. Actually then we end up creating self-inflicted merge conflict here with next. So let's wait a bit on this one as it's harmless. J.D. can you please rebase this against current Linux next? Note the recent unit name and unit address fixes for warnings with make W=1 dtbs. Regards, Tony