From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48629) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b04d6-0005zg-D6 for qemu-devel@nongnu.org; Tue, 10 May 2016 06:11:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b04d3-0002Td-0p for qemu-devel@nongnu.org; Tue, 10 May 2016 06:11:04 -0400 Received: from mx1.redhat.com ([209.132.183.28]:43305) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b04d2-0002TT-Rs for qemu-devel@nongnu.org; Tue, 10 May 2016 06:11:00 -0400 Date: Tue, 10 May 2016 18:10:53 +0800 From: Peter Xu Message-ID: <20160510101053.GD22463@pxdev.xzpeter.org> References: <1461055122-32378-1-git-send-email-peterx@redhat.com> <571DA823.1030003@web.de> <20160425071806.GF3261@pxdev.xzpeter.org> <571DC61C.9020006@web.de> <20160426073426.GD28545@pxdev.xzpeter.org> <57307B78.9030000@redhat.com> <20160510060919.GB14799@pxdev.xzpeter.org> <5731A29A.7040007@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <5731A29A.7040007@redhat.com> Subject: Re: [Qemu-devel] [PATCH v4 00/16] IOMMU: Enable interrupt remapping for Intel IOMMU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: Jan Kiszka , qemu-devel@nongnu.org, imammedo@redhat.com, rth@twiddle.net, ehabkost@redhat.com, jasowang@redhat.com, marcel@redhat.com, mst@redhat.com, rkrcmar@redhat.com, alex.williamson@redhat.com, wexu@redhat.com On Tue, May 10, 2016 at 10:58:02AM +0200, Paolo Bonzini wrote: > > > On 10/05/2016 08:09, Peter Xu wrote: > > On Mon, May 09, 2016 at 01:58:48PM +0200, Paolo Bonzini wrote: > >> Is this enough too? > >> > >> diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c > >> index 378e663..2443a35 100644 > >> --- a/hw/intc/ioapic.c > >> +++ b/hw/intc/ioapic.c > >> @@ -72,6 +72,7 @@ static void ioapic_service(IOAPICCommonState *s) > >> (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK; > >> if (trig_mode == IOAPIC_TRIGGER_EDGE) { > >> s->irr &= ~mask; > >> + s->ioredtbl[i] &= ~IOAPIC_LVT_REMOTE_IRR; > >> } else { > >> coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR; > >> s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR; > > > > I gave it a quick shot on this but still got the warning. :( > > > > I _guess_ the problem is: the above change is in the "if" block of > > (s->irr & mask), when the kernel plays the trick of EOI, the irq > > should be pulled down already by the device (or say, irr bit is > > cleared). So it does not go into this "if" block. > > No problem; feel free to send the other patch separately and I'll take > care of merging it. Otherwise mst can merge it too. Indeed these two patches are totally independent from the IOMMU content. I'll send them seperately then. :) Thanks, -- peterx