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Date: Thu, 19 May 2016 16:26:49 +0100
From: Liviu Dudau <Liviu.Dudau@arm.com>
To: David Airlie <airlied@linux.ie>,
        DRI devel <dri-devel@lists.freedesktop.org>,
        LKML <linux-kernel@vger.kernel.org>, Daniel Vetter <daniel@ffwll.ch>,
        Brian Starkey <Brian.Starkey@arm.com>,
        David Brown <David.Brown@arm.com>
Subject: Re: [PATCH v2 2/3] drm/arm: Add support for Mali Display Processors
Message-ID: <20160519152648.GG23566@e106497-lin.cambridge.arm.com>
References: <1461593964-27722-1-git-send-email-Liviu.Dudau@arm.com>
 <1461593964-27722-3-git-send-email-Liviu.Dudau@arm.com>
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On Mon, Apr 25, 2016 at 03:19:23PM +0100, Liviu Dudau wrote:
> Add support for the new family of Display Processors from ARM Ltd.
> This commit adds basic support for Mali DP500, DP550 and DP650
> parts, with only the display engine being supported at the moment.
> 
> Cc: David Brown <David.Brown@arm.com>
> Cc: Brian Starkey <Brian.Starkey@arm.com>
> 
> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>

Hello,

I'm fully aware that the merge window is open and people are busy, however if
any of the DRM sub-maintainers could provide some Acks or Reviewed-bys I would
really appreciate it.

I plan to make the code available under a new branch to go into linux-next next
week.

Best regards,
Liviu

> ---
>  drivers/gpu/drm/arm/Kconfig         |  16 +
>  drivers/gpu/drm/arm/Makefile        |   2 +
>  drivers/gpu/drm/arm/malidp_crtc.c   | 259 ++++++++++++
>  drivers/gpu/drm/arm/malidp_drv.c    | 538 +++++++++++++++++++++++++
>  drivers/gpu/drm/arm/malidp_drv.h    |  54 +++
>  drivers/gpu/drm/arm/malidp_hw.c     | 774 ++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/arm/malidp_hw.h     | 189 +++++++++
>  drivers/gpu/drm/arm/malidp_planes.c | 337 ++++++++++++++++
>  drivers/gpu/drm/arm/malidp_regs.h   | 172 ++++++++
>  9 files changed, 2341 insertions(+)
>  create mode 100644 drivers/gpu/drm/arm/malidp_crtc.c
>  create mode 100644 drivers/gpu/drm/arm/malidp_drv.c
>  create mode 100644 drivers/gpu/drm/arm/malidp_drv.h
>  create mode 100644 drivers/gpu/drm/arm/malidp_hw.c
>  create mode 100644 drivers/gpu/drm/arm/malidp_hw.h
>  create mode 100644 drivers/gpu/drm/arm/malidp_planes.c
>  create mode 100644 drivers/gpu/drm/arm/malidp_regs.h
> 
> diff --git a/drivers/gpu/drm/arm/Kconfig b/drivers/gpu/drm/arm/Kconfig
> index eaed454..1b29065 100644
> --- a/drivers/gpu/drm/arm/Kconfig
> +++ b/drivers/gpu/drm/arm/Kconfig
> @@ -25,3 +25,19 @@ config DRM_HDLCD_SHOW_UNDERRUN
>  	  Enable this option to show in red colour the pixels that the
>  	  HDLCD device did not fetch from framebuffer due to underrun
>  	  conditions.
> +
> +config DRM_MALI_DISPLAY
> +	tristate "ARM Mali Display Processor"
> +	depends on DRM && OF && (ARM || ARM64)
> +	depends on COMMON_CLK
> +	select DRM_ARM
> +	select DRM_KMS_HELPER
> +	select DRM_KMS_CMA_HELPER
> +	select DRM_GEM_CMA_HELPER
> +	select VIDEOMODE_HELPERS
> +	help
> +	  Choose this option if you want to compile the ARM Mali Display
> +	  Processor driver. It supports the DP500, DP550 and DP650 variants
> +	  of the hardware.
> +
> +	  If compiled as a module it will be called mali-dp.
> diff --git a/drivers/gpu/drm/arm/Makefile b/drivers/gpu/drm/arm/Makefile
> index 89dcb7b..bb8b158 100644
> --- a/drivers/gpu/drm/arm/Makefile
> +++ b/drivers/gpu/drm/arm/Makefile
> @@ -1,2 +1,4 @@
>  hdlcd-y := hdlcd_drv.o hdlcd_crtc.o
>  obj-$(CONFIG_DRM_HDLCD)	+= hdlcd.o
> +mali-dp-y := malidp_drv.o malidp_hw.o malidp_planes.o malidp_crtc.o
> +obj-$(CONFIG_DRM_MALI_DISPLAY)	+= mali-dp.o
> diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c
> new file mode 100644
> index 0000000..12893d0
> --- /dev/null
> +++ b/drivers/gpu/drm/arm/malidp_crtc.c
> @@ -0,0 +1,259 @@
> +/*
> + * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
> + * Author: Liviu Dudau <Liviu.Dudau@arm.com>
> + *
> + * This program is free software and is provided to you under the terms of the
> + * GNU General Public License version 2 as published by the Free Software
> + * Foundation, and any use by you of this program is subject to the terms
> + * of such GNU licence.
> + *
> + * ARM Mali DP500/DP550/DP650 driver (crtc operations)
> + */
> +
> +#include <drm/drmP.h>
> +#include <drm/drm_atomic.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <linux/clk.h>
> +#include <video/videomode.h>
> +
> +#include "malidp_drv.h"
> +#include "malidp_hw.h"
> +
> +static bool malidp_crtc_mode_fixup(struct drm_crtc *crtc,
> +				   const struct drm_display_mode *mode,
> +				   struct drm_display_mode *adjusted_mode)
> +{
> +	struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
> +	struct malidp_hw_device *hwdev = malidp->dev;
> +
> +	/*
> +	 * check that the hardware can drive the required clock rate,
> +	 * but skip the check if the clock is meant to be disabled (req_rate = 0)
> +	 */
> +	long rate, req_rate = mode->crtc_clock * 1000;
> +
> +	if (req_rate) {
> +		rate = clk_round_rate(hwdev->mclk, req_rate);
> +		if (rate < req_rate) {
> +			DRM_DEBUG_DRIVER("mclk clock unable to reach %d kHz\n",
> +					 mode->crtc_clock);
> +			return false;
> +		}
> +
> +		rate = clk_round_rate(hwdev->pxlclk, req_rate);
> +		if (rate != req_rate) {
> +			DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n",
> +					 req_rate);
> +			return false;
> +		}
> +	}
> +
> +	return true;
> +}
> +
> +static void malidp_crtc_enable(struct drm_crtc *crtc)
> +{
> +	struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
> +	struct malidp_hw_device *hwdev = malidp->dev;
> +	struct videomode vm;
> +
> +	drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm);
> +
> +	clk_prepare_enable(hwdev->pxlclk);
> +
> +	/* mclk needs to be set to the same or higher rate than pxlclk */
> +	clk_set_rate(hwdev->mclk, crtc->state->adjusted_mode.crtc_clock * 1000);
> +	clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000);
> +
> +	hwdev->modeset(hwdev, &vm);
> +	hwdev->leave_config_mode(hwdev);
> +}
> +
> +static void malidp_crtc_disable(struct drm_crtc *crtc)
> +{
> +	struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
> +	struct malidp_hw_device *hwdev = malidp->dev;
> +
> +	/*
> +	 * avoid disabling already disabled clocks and hardware
> +	 * (as is the case at device probe time)
> +	 */
> +	if (crtc->state->active) {
> +		hwdev->enter_config_mode(hwdev);
> +		clk_disable_unprepare(hwdev->pxlclk);
> +	}
> +}
> +
> +static int malidp_crtc_atomic_check(struct drm_crtc *crtc,
> +				    struct drm_crtc_state *state)
> +{
> +	struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
> +	struct malidp_hw_device *hwdev = malidp->dev;
> +	struct drm_plane *plane;
> +	struct drm_plane_state *pstate;
> +	u32 rot_mem_free, rot_mem_usable;
> +	int rotated_planes = 0;
> +
> +	/*
> +	 * check if there is enough rotation memory available for planes
> +	 * that need 90° and 270° rotation. Each plane has set its required
> +	 * memory size in the ->plane_check() callback, here we only make
> +	 * sure that the sums are less that the total usable memory.
> +	 *
> +	 * The rotation memory allocation algorithm (for each plane):
> +	 *  a. If no more rotated planes exist, all remaining rotate
> +	 *     memory in the bank is available for use by the plane.
> +	 *  b. If other rotated planes exist, and plane's layer ID is
> +	 *     DE_VIDEO1, it can use all the memory from first bank if
> +	 *     secondary rotation memory bank is available, otherwise it can
> +	 *     use up to half the bank's memory.
> +	 *  c. If other rotated planes exist, and plane's layer ID is not
> +	 *     DE_VIDEO1, it can use half of the available memory
> +	 *
> +	 * Note: this algorithm assumes that the order in which the planes are
> +	 * checked always has DE_VIDEO1 plane first in the list if it is
> +	 * rotated. Because that is how we create the planes in the first
> +	 * place, under current DRM version things work, but if ever the order
> +	 * in which drm_atomic_crtc_state_for_each_plane() iterates over planes
> +	 * changes, we need to pre-sort the planes before validation.
> +	 */
> +
> +	/* first count the number of rotated planes */
> +	drm_atomic_crtc_state_for_each_plane(plane, state) {
> +		pstate = drm_atomic_get_plane_state(state->state, plane);
> +		if (pstate->rotation & MALIDP_ROTATED_MASK)
> +			rotated_planes++;
> +	}
> +
> +	rot_mem_free = hwdev->rotation_memory[0];
> +	/*
> +	 * if we have more than 1 plane using rotation memory, use the second
> +	 * block of rotation memory as well
> +	 */
> +	if (rotated_planes > 1)
> +		rot_mem_free += hwdev->rotation_memory[1];
> +
> +	/* now validate the rotation memory requirements */
> +	drm_atomic_crtc_state_for_each_plane(plane, state) {
> +		struct malidp_plane *mp = to_malidp_plane(plane);
> +
> +		pstate = drm_atomic_get_plane_state(state->state, plane);
> +		if (pstate->rotation & MALIDP_ROTATED_MASK) {
> +			/* process current plane */
> +			rotated_planes--;
> +
> +			if (!rotated_planes) {
> +				/* no more rotated planes, we can use what's left */
> +				rot_mem_usable = rot_mem_free;
> +			} else {
> +				if ((mp->layer->id != DE_VIDEO1) ||
> +				    (hwdev->rotation_memory[1] == 0))
> +					rot_mem_usable = rot_mem_free / 2;
> +				else
> +					rot_mem_usable = hwdev->rotation_memory[0];
> +			}
> +
> +			rot_mem_free -= rot_mem_usable;
> +
> +			if (mp->rotmem_size > rot_mem_usable)
> +				return -EINVAL;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static void malidp_crtc_atomic_begin(struct drm_crtc *crtc,
> +				     struct drm_crtc_state *old_state)
> +{
> +	struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
> +
> +	if (crtc->state->event) {
> +		struct drm_pending_vblank_event *event = crtc->state->event;
> +		unsigned long flags;
> +
> +		crtc->state->event = NULL;
> +		event->pipe = drm_crtc_index(crtc);
> +
> +		WARN_ON(drm_crtc_vblank_get(crtc) != 0);
> +
> +		spin_lock_irqsave(&crtc->dev->event_lock, flags);
> +		list_add_tail(&event->base.link, &malidp->event_list);
> +		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
> +	}
> +}
> +
> +static void malidp_crtc_atomic_flush(struct drm_crtc *crtc,
> +				     struct drm_crtc_state *old_state)
> +{
> +	struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
> +	struct drm_device *drm = crtc->dev;
> +	int ret = malidp_set_and_wait_config_valid(drm);
> +
> +	if (!ret) {
> +		unsigned long flags;
> +		struct drm_pending_vblank_event *e;
> +
> +		spin_lock_irqsave(&drm->event_lock, flags);
> +		e = list_first_entry_or_null(&malidp->event_list, typeof(*e),
> +					     base.link);
> +		if (e) {
> +			list_del(&e->base.link);
> +			drm_crtc_send_vblank_event(&malidp->crtc, e);
> +			drm_crtc_vblank_put(&malidp->crtc);
> +		}
> +		spin_unlock_irqrestore(&drm->event_lock, flags);
> +	} else {
> +		DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");
> +	}
> +}
> +
> +static const struct drm_crtc_helper_funcs malidp_crtc_helper_funcs = {
> +	.mode_fixup = malidp_crtc_mode_fixup,
> +	.enable = malidp_crtc_enable,
> +	.disable = malidp_crtc_disable,
> +	.atomic_check = malidp_crtc_atomic_check,
> +	.atomic_begin = malidp_crtc_atomic_begin,
> +	.atomic_flush = malidp_crtc_atomic_flush,
> +};
> +
> +static const struct drm_crtc_funcs malidp_crtc_funcs = {
> +	.destroy = drm_crtc_cleanup,
> +	.set_config = drm_atomic_helper_set_config,
> +	.page_flip = drm_atomic_helper_page_flip,
> +	.reset = drm_atomic_helper_crtc_reset,
> +	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
> +	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
> +};
> +
> +int malidp_crtc_init(struct drm_device *drm)
> +{
> +	struct malidp_drm *malidp = drm->dev_private;
> +	struct drm_plane *primary = NULL, *plane;
> +	int ret;
> +
> +	drm_for_each_plane(plane, drm) {
> +		if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
> +			primary = plane;
> +			break;
> +		}
> +	}
> +
> +	if (!primary) {
> +		DRM_ERROR("no primary plane found\n");
> +		return -EINVAL;
> +	}
> +
> +	ret = drm_crtc_init_with_planes(drm, &malidp->crtc, primary, NULL,
> +					&malidp_crtc_funcs, NULL);
> +
> +	if (ret) {
> +		malidp_de_planes_destroy(drm);
> +		return ret;
> +	}
> +
> +	drm_crtc_helper_add(&malidp->crtc, &malidp_crtc_helper_funcs);
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c
> new file mode 100644
> index 0000000..10ffb81
> --- /dev/null
> +++ b/drivers/gpu/drm/arm/malidp_drv.c
> @@ -0,0 +1,538 @@
> +/*
> + * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
> + * Author: Liviu Dudau <Liviu.Dudau@arm.com>
> + *
> + * This program is free software and is provided to you under the terms of the
> + * GNU General Public License version 2 as published by the Free Software
> + * Foundation, and any use by you of this program is subject to the terms
> + * of such GNU licence.
> + *
> + * ARM Mali DP500/DP550/DP650 KMS/DRM driver
> + */
> +
> +#include <linux/module.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_graph.h>
> +#include <linux/of_reserved_mem.h>
> +
> +#include <drm/drmP.h>
> +#include <drm/drm_atomic.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_fb_helper.h>
> +#include <drm/drm_fb_cma_helper.h>
> +#include <drm/drm_gem_cma_helper.h>
> +#include <drm/drm_of.h>
> +
> +#include "malidp_drv.h"
> +#include "malidp_regs.h"
> +#include "malidp_hw.h"
> +
> +#define MALIDP_CONF_VALID_TIMEOUT	250
> +
> +/*
> + * set the "config valid" bit and wait until the hardware
> + * acts on it
> + */
> +int malidp_set_and_wait_config_valid(struct drm_device *drm)
> +{
> +	struct malidp_drm *malidp = drm->dev_private;
> +	struct malidp_hw_device *hwdev = malidp->dev;
> +	int ret;
> +
> +	hwdev->set_config_valid(hwdev);
> +	/* don't wait for config_valid flag if we are in config mode */
> +	if (hwdev->in_config_mode(hwdev))
> +		return 0;
> +
> +	ret = wait_event_interruptible_timeout(malidp->wq,
> +			atomic_read(&malidp->config_valid) == 1,
> +			msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT));
> +
> +	return (ret > 0) ? 0 : -ETIMEDOUT;
> +}
> +
> +static void malidp_output_poll_changed(struct drm_device *drm)
> +{
> +	struct malidp_drm *malidp = drm->dev_private;
> +
> +	if (malidp->fbdev)
> +		drm_fbdev_cma_hotplug_event(malidp->fbdev);
> +}
> +
> +static void malidp_atomic_complete(struct drm_device *drm,
> +				   struct drm_atomic_state *old_state)
> +{
> +	/* ToDo: wait_for_fences(drm, old_state); */
> +
> +	drm_atomic_helper_commit_modeset_disables(drm, old_state);
> +	drm_atomic_helper_commit_planes(drm, old_state, false);
> +	drm_atomic_helper_commit_modeset_enables(drm, old_state);
> +
> +	drm_atomic_helper_wait_for_vblanks(drm, old_state);
> +
> +	drm_atomic_helper_cleanup_planes(drm, old_state);
> +	drm_atomic_state_free(old_state);
> +}
> +
> +static void malidp_atomic_work(struct work_struct *work)
> +{
> +	struct malidp_drm *malidp = container_of(work, struct malidp_drm,
> +						 commit.work);
> +
> +	malidp_atomic_complete(malidp->commit.state->dev,
> +			       malidp->commit.state);
> +}
> +
> +static int malidp_atomic_commit(struct drm_device *drm,
> +				struct drm_atomic_state *state,
> +				bool async)
> +{
> +	struct malidp_drm *malidp = drm->dev_private;
> +	int err;
> +
> +	err = drm_atomic_helper_prepare_planes(drm, state);
> +	if (err)
> +		return err;
> +
> +	if (async && !list_empty(&malidp->commit.work.entry)) {
> +		/* pending commits found, bail out */
> +		return -EBUSY;
> +	}
> +
> +	mutex_lock(&malidp->commit.lock);
> +	flush_work(&malidp->commit.work);
> +
> +	/*
> +	 * The point of no return awaits here. After this we commit
> +	 * on software side to handle the new state
> +	 */
> +	drm_atomic_helper_swap_state(drm, state);
> +
> +	malidp->commit.state = state;
> +
> +	if (async)
> +		schedule_work(&malidp->commit.work);
> +	else
> +		malidp_atomic_complete(drm, state);
> +
> +	mutex_unlock(&malidp->commit.lock);
> +	return 0;
> +}
> +
> +static const struct drm_mode_config_funcs malidp_mode_config_funcs = {
> +	.fb_create = drm_fb_cma_create,
> +	.output_poll_changed = malidp_output_poll_changed,
> +	.atomic_check = drm_atomic_helper_check,
> +	.atomic_commit = malidp_atomic_commit,
> +};
> +
> +static int malidp_enable_vblank(struct drm_device *drm, unsigned int crtc)
> +{
> +	return 0;
> +}
> +
> +static void malidp_disable_vblank(struct drm_device *drm, unsigned int pipe)
> +{
> +}
> +
> +static int malidp_init(struct drm_device *drm)
> +{
> +	int ret;
> +	struct malidp_drm *malidp = drm->dev_private;
> +	struct malidp_hw_device *hwdev = malidp->dev;
> +
> +	drm_mode_config_init(drm);
> +
> +	drm->mode_config.min_width = hwdev->min_line_size;
> +	drm->mode_config.min_height = hwdev->min_line_size;
> +	drm->mode_config.max_width = hwdev->max_line_size;
> +	drm->mode_config.max_height = hwdev->max_line_size;
> +	drm->mode_config.funcs = &malidp_mode_config_funcs;
> +
> +	ret = malidp_de_planes_init(drm);
> +	if (ret < 0) {
> +		DRM_ERROR("Failed to initialise planes\n");
> +		goto plane_init_fail;
> +	}
> +
> +	ret = malidp_crtc_init(drm);
> +	if (ret) {
> +		DRM_ERROR("Failed to initialise CRTC\n");
> +		goto crtc_init_fail;
> +	}
> +
> +	return 0;
> +
> +crtc_init_fail:
> +	malidp_de_planes_destroy(drm);
> +plane_init_fail:
> +	drm_mode_config_cleanup(drm);
> +
> +	return ret;
> +}
> +
> +static int malidp_irq_init(struct platform_device *pdev)
> +{
> +	int irq_de, irq_se, ret = 0;
> +	struct drm_device *drm = dev_get_drvdata(&pdev->dev);
> +
> +	/* fetch the interrupts from DT */
> +	irq_de = platform_get_irq_byname(pdev, "DE");
> +	if (irq_de < 0) {
> +		DRM_ERROR("no 'DE' IRQ specified!\n");
> +		return irq_de;
> +	}
> +	irq_se = platform_get_irq_byname(pdev, "SE");
> +	if (irq_se < 0) {
> +		DRM_ERROR("no 'SE' IRQ specified!\n");
> +		return irq_se;
> +	}
> +
> +	ret = malidp_de_irq_init(drm, irq_de);
> +	if (ret)
> +		return ret;
> +
> +	ret = malidp_se_irq_init(drm, irq_se);
> +	if (ret) {
> +		malidp_de_irq_cleanup(drm);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static void malidp_lastclose(struct drm_device *drm)
> +{
> +	struct malidp_drm *malidp = drm->dev_private;
> +
> +	drm_fbdev_cma_restore_mode(malidp->fbdev);
> +}
> +
> +static const struct file_operations fops = {
> +	.owner = THIS_MODULE,
> +	.open = drm_open,
> +	.release = drm_release,
> +	.unlocked_ioctl = drm_ioctl,
> +#ifdef CONFIG_COMPAT
> +	.compat_ioctl = drm_compat_ioctl,
> +#endif
> +	.poll = drm_poll,
> +	.read = drm_read,
> +	.llseek = noop_llseek,
> +	.mmap = drm_gem_cma_mmap,
> +};
> +
> +static struct drm_driver malidp_driver = {
> +	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |
> +			   DRIVER_PRIME,
> +	.lastclose = malidp_lastclose,
> +	.get_vblank_counter = drm_vblank_no_hw_counter,
> +	.enable_vblank = malidp_enable_vblank,
> +	.disable_vblank = malidp_disable_vblank,
> +	.gem_free_object = drm_gem_cma_free_object,
> +	.gem_vm_ops = &drm_gem_cma_vm_ops,
> +	.dumb_create = drm_gem_cma_dumb_create,
> +	.dumb_map_offset = drm_gem_cma_dumb_map_offset,
> +	.dumb_destroy = drm_gem_dumb_destroy,
> +	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> +	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> +	.gem_prime_export = drm_gem_prime_export,
> +	.gem_prime_import = drm_gem_prime_import,
> +	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> +	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> +	.gem_prime_vmap = drm_gem_cma_prime_vmap,
> +	.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
> +	.gem_prime_mmap = drm_gem_cma_prime_mmap,
> +	.fops = &fops,
> +	.name = "mali-dp",
> +	.desc = "ARM Mali Display Processor driver",
> +	.date = "20160106",
> +	.major = 1,
> +	.minor = 0,
> +};
> +
> +static const struct of_device_id  malidp_drm_of_match[] = {
> +	{
> +		.compatible = "arm,mali-dp500",
> +		.data = &malidp_device[MALIDP_500]
> +	},
> +	{
> +		.compatible = "arm,mali-dp550",
> +		.data = &malidp_device[MALIDP_550]
> +	},
> +	{
> +		.compatible = "arm,mali-dp650",
> +		.data = &malidp_device[MALIDP_650]
> +	},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, malidp_drm_of_match);
> +
> +#define MAX_OUTPUT_CHANNELS	3
> +
> +static int malidp_bind(struct device *dev)
> +{
> +	struct resource *res;
> +	struct drm_device *drm;
> +	struct malidp_drm *malidp;
> +	struct malidp_hw_device *hwdev;
> +	struct platform_device *pdev = to_platform_device(dev);
> +	/* number of lines for the R, G and B output */
> +	u8 output_width[MAX_OUTPUT_CHANNELS];
> +	int ret = 0, i;
> +	u32 version, out_depth = 0;
> +
> +	malidp = devm_kzalloc(dev, sizeof(*malidp), GFP_KERNEL);
> +	if (!malidp)
> +		return -ENOMEM;
> +
> +	hwdev = devm_kzalloc(dev, sizeof(*hwdev), GFP_KERNEL);
> +	if (!hwdev)
> +		return -ENOMEM;
> +
> +	/*
> +	 * copy the associated data from malidp_drm_of_match to avoid
> +	 * having to keep a reference to the OF node after binding
> +	 */
> +	memcpy(hwdev, of_device_get_match_data(dev), sizeof(*hwdev));
> +	malidp->dev = hwdev;
> +
> +	INIT_LIST_HEAD(&malidp->event_list);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	hwdev->regs = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(hwdev->regs)) {
> +		DRM_ERROR("Failed to map control registers area\n");
> +		return PTR_ERR(hwdev->regs);
> +	}
> +
> +	hwdev->pclk = devm_clk_get(dev, "pclk");
> +	if (IS_ERR(hwdev->pclk))
> +		return PTR_ERR(hwdev->pclk);
> +
> +	hwdev->aclk = devm_clk_get(dev, "aclk");
> +	if (IS_ERR(hwdev->aclk))
> +		return PTR_ERR(hwdev->aclk);
> +
> +	hwdev->mclk = devm_clk_get(dev, "mclk");
> +	if (IS_ERR(hwdev->mclk))
> +		return PTR_ERR(hwdev->mclk);
> +
> +	hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
> +	if (IS_ERR(hwdev->pxlclk))
> +		return PTR_ERR(hwdev->pxlclk);
> +
> +	/* Get the optional framebuffer memory resource */
> +	ret = of_reserved_mem_device_init(dev);
> +	if (ret && ret != -ENODEV)
> +		return ret;
> +
> +	drm = drm_dev_alloc(&malidp_driver, dev);
> +	if (!drm) {
> +		ret = -ENOMEM;
> +		goto alloc_fail;
> +	}
> +
> +	/* Enable APB clock in order to get access to the registers */
> +	clk_prepare_enable(hwdev->pclk);
> +	/*
> +	 * Enable AXI clock and main clock so that prefetch can start once
> +	 * the registers are set
> +	 */
> +	clk_prepare_enable(hwdev->aclk);
> +	clk_prepare_enable(hwdev->mclk);
> +
> +	ret = hwdev->query_hw(hwdev);
> +	if (ret) {
> +		DRM_ERROR("Invalid HW configuration\n");
> +		goto query_hw_fail;
> +	}
> +
> +	version = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_DE_CORE_ID);
> +	DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16,
> +		 (version >> 12) & 0xf, (version >> 8) & 0xf);
> +
> +	/* set the number of lines used for output of RGB data */
> +	ret = of_property_read_u8_array(dev->of_node,
> +					"arm,malidp-output-port-lines",
> +					output_width, MAX_OUTPUT_CHANNELS);
> +	if (ret)
> +		goto query_hw_fail;
> +
> +	for (i = 0; i < MAX_OUTPUT_CHANNELS; i++)
> +		out_depth = (out_depth << 8) | (output_width[i] & 0xf);
> +	malidp_hw_write(hwdev, out_depth, hwdev->map.out_depth_base);
> +
> +	drm->dev_private = malidp;
> +	dev_set_drvdata(dev, drm);
> +	atomic_set(&malidp->config_valid, 0);
> +	init_waitqueue_head(&malidp->wq);
> +
> +	mutex_init(&malidp->commit.lock);
> +	INIT_WORK(&malidp->commit.work, malidp_atomic_work);
> +
> +	ret = malidp_init(drm);
> +	if (ret < 0)
> +		goto init_fail;
> +
> +	ret = drm_dev_register(drm, 0);
> +	if (ret)
> +		goto register_fail;
> +
> +	/* Set the CRTC's port so that the encoder component can find it */
> +	malidp->crtc.port = of_graph_get_next_endpoint(dev->of_node, NULL);
> +
> +	ret = component_bind_all(dev, drm);
> +	of_node_put(malidp->crtc.port);
> +
> +	if (ret) {
> +		DRM_ERROR("Failed to bind all components\n");
> +		goto bind_fail;
> +	}
> +
> +	ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
> +	if (ret < 0) {
> +		DRM_ERROR("failed to initialise vblank\n");
> +		goto vblank_fail;
> +	}
> +	drm->vblank_disable_allowed = true;
> +
> +	ret = malidp_irq_init(pdev);
> +	if (ret < 0)
> +		goto irq_init_fail;
> +
> +	drm_mode_config_reset(drm);
> +
> +	drm_helper_disable_unused_functions(drm);
> +	malidp->fbdev = drm_fbdev_cma_init(drm, 32, drm->mode_config.num_crtc,
> +					   drm->mode_config.num_connector);
> +
> +	if (IS_ERR(malidp->fbdev)) {
> +		ret = PTR_ERR(malidp->fbdev);
> +		malidp->fbdev = NULL;
> +		goto fbdev_fail;
> +	}
> +
> +	drm_kms_helper_poll_init(drm);
> +	return 0;
> +
> +fbdev_fail:
> +	malidp_se_irq_cleanup(drm);
> +	malidp_de_irq_cleanup(drm);
> +irq_init_fail:
> +	drm_vblank_cleanup(drm);
> +vblank_fail:
> +	component_unbind_all(dev, drm);
> +bind_fail:
> +	drm_dev_unregister(drm);
> +register_fail:
> +	malidp_de_planes_destroy(drm);
> +	drm_mode_config_cleanup(drm);
> +init_fail:
> +	drm->dev_private = NULL;
> +	dev_set_drvdata(dev, NULL);
> +query_hw_fail:
> +	clk_disable_unprepare(hwdev->mclk);
> +	clk_disable_unprepare(hwdev->aclk);
> +	clk_disable_unprepare(hwdev->pclk);
> +	drm_dev_unref(drm);
> +alloc_fail:
> +	of_reserved_mem_device_release(dev);
> +
> +	return ret;
> +}
> +
> +static void malidp_unbind(struct device *dev)
> +{
> +	struct drm_device *drm = dev_get_drvdata(dev);
> +	struct malidp_drm *malidp = drm->dev_private;
> +	struct malidp_hw_device *hwdev = malidp->dev;
> +
> +	if (malidp->fbdev) {
> +		drm_fbdev_cma_fini(malidp->fbdev);
> +		malidp->fbdev = NULL;
> +	}
> +	drm_kms_helper_poll_fini(drm);
> +	malidp_se_irq_cleanup(drm);
> +	malidp_de_irq_cleanup(drm);
> +	drm_vblank_cleanup(drm);
> +	component_unbind_all(dev, drm);
> +	drm_dev_unregister(drm);
> +	malidp_de_planes_destroy(drm);
> +	drm_mode_config_cleanup(drm);
> +	drm->dev_private = NULL;
> +	dev_set_drvdata(dev, NULL);
> +	clk_disable_unprepare(hwdev->mclk);
> +	clk_disable_unprepare(hwdev->aclk);
> +	clk_disable_unprepare(hwdev->pclk);
> +	drm_dev_unref(drm);
> +	of_reserved_mem_device_release(dev);
> +}
> +
> +static const struct component_master_ops malidp_master_ops = {
> +	.bind = malidp_bind,
> +	.unbind = malidp_unbind,
> +};
> +
> +static int malidp_compare_dev(struct device *dev, void *data)
> +{
> +	struct device_node *np = data;
> +
> +	return dev->of_node == np;
> +}
> +
> +static int malidp_platform_probe(struct platform_device *pdev)
> +{
> +	struct device_node *port, *ep;
> +	struct component_match *match = NULL;
> +
> +	if (!pdev->dev.of_node)
> +		return -ENODEV;
> +
> +	/* there is only one output port inside each device, find it */
> +	ep = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);
> +	if (!ep)
> +		return -ENODEV;
> +
> +	if (!of_device_is_available(ep)) {
> +		of_node_put(ep);
> +		return -ENODEV;
> +	}
> +
> +	/* add the remote encoder port as component */
> +	port = of_graph_get_remote_port_parent(ep);
> +	of_node_put(ep);
> +	if (!port || !of_device_is_available(port)) {
> +		of_node_put(port);
> +		return -EAGAIN;
> +	}
> +
> +	component_match_add(&pdev->dev, &match, malidp_compare_dev, port);
> +	return component_master_add_with_match(&pdev->dev, &malidp_master_ops,
> +					       match);
> +}
> +
> +static int malidp_platform_remove(struct platform_device *pdev)
> +{
> +	component_master_del(&pdev->dev, &malidp_master_ops);
> +	return 0;
> +}
> +
> +static struct platform_driver malidp_platform_driver = {
> +	.probe		= malidp_platform_probe,
> +	.remove		= malidp_platform_remove,
> +	.driver	= {
> +		.name = "mali-dp",
> +		.of_match_table	= malidp_drm_of_match,
> +	},
> +};
> +
> +module_platform_driver(malidp_platform_driver);
> +
> +MODULE_AUTHOR("Liviu Dudau <Liviu.Dudau@arm.com>");
> +MODULE_DESCRIPTION("ARM Mali DP DRM driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/arm/malidp_drv.h b/drivers/gpu/drm/arm/malidp_drv.h
> new file mode 100644
> index 0000000..effd3be
> --- /dev/null
> +++ b/drivers/gpu/drm/arm/malidp_drv.h
> @@ -0,0 +1,54 @@
> +/*
> + * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
> + * Author: Liviu Dudau <Liviu.Dudau@arm.com>
> + *
> + * This program is free software and is provided to you under the terms of the
> + * GNU General Public License version 2 as published by the Free Software
> + * Foundation, and any use by you of this program is subject to the terms
> + * of such GNU licence.
> + *
> + * ARM Mali DP500/DP550/DP650 KMS/DRM driver structures
> + */
> +
> +#ifndef __MALIDP_DRV_H__
> +#define __MALIDP_DRV_H__
> +
> +#include <linux/mutex.h>
> +#include <linux/wait.h>
> +#include "malidp_hw.h"
> +
> +struct malidp_drm {
> +	struct malidp_hw_device *dev;
> +	struct drm_fbdev_cma *fbdev;
> +	struct list_head event_list;
> +	struct drm_crtc crtc;
> +	wait_queue_head_t wq;
> +	struct {
> +		struct drm_atomic_state *state;
> +		struct work_struct work;
> +		struct mutex lock;
> +	} commit;
> +	atomic_t config_valid;
> +};
> +
> +#define crtc_to_malidp_device(x) container_of(x, struct malidp_drm, crtc)
> +
> +struct malidp_plane {
> +	struct drm_plane base;
> +	struct malidp_hw_device *hwdev;
> +	const struct malidp_layer *layer;
> +	/* size of the required rotation memory when plane is rotated */
> +	u32 rotmem_size;
> +};
> +
> +#define to_malidp_plane(x) container_of(x, struct malidp_plane, base)
> +
> +int malidp_set_and_wait_config_valid(struct drm_device *drm);
> +int malidp_de_planes_init(struct drm_device *drm);
> +void malidp_de_planes_destroy(struct drm_device *drm);
> +int malidp_crtc_init(struct drm_device *drm);
> +
> +/* often used combination of rotational bits */
> +#define MALIDP_ROTATED_MASK	(BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))
> +
> +#endif  /* __MALIDP_DRV_H__ */
> diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c
> new file mode 100644
> index 0000000..22519f4
> --- /dev/null
> +++ b/drivers/gpu/drm/arm/malidp_hw.c
> @@ -0,0 +1,774 @@
> +/*
> + * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
> + * Author: Liviu Dudau <Liviu.Dudau@arm.com>
> + *
> + * This program is free software and is provided to you under the terms of the
> + * GNU General Public License version 2 as published by the Free Software
> + * Foundation, and any use by you of this program is subject to the terms
> + * of such GNU licence.
> + *
> + * ARM Mali DP500/DP550/DP650 hardware manipulation routines. This is where
> + * the difference between various versions of the hardware is being dealt with
> + * in an attempt to provide to the rest of the driver code a unified view
> + */
> +
> +#include <linux/types.h>
> +#include <linux/io.h>
> +#include <drm/drmP.h>
> +#include <video/videomode.h>
> +#include <video/display_timing.h>
> +
> +#include "malidp_drv.h"
> +#include "malidp_hw.h"
> +#include "malidp_regs.h"
> +
> +static const struct malidp_input_format malidp500_de_formats[] = {
> +	/*    layers supporting the format,     internal id,      fourcc */
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  0, DRM_FORMAT_ARGB2101010 },
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  1, DRM_FORMAT_ABGR2101010 },
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  2, DRM_FORMAT_ARGB8888 },
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  3, DRM_FORMAT_ABGR8888 },
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  4, DRM_FORMAT_XRGB8888 },
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  5, DRM_FORMAT_XBGR8888 },
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  6, DRM_FORMAT_RGB888 },
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  7, DRM_FORMAT_BGR888 },
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  8, DRM_FORMAT_RGBA5551 },
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2,  9, DRM_FORMAT_ABGR1555 },
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 10, DRM_FORMAT_RGB565 },
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 11, DRM_FORMAT_BGR565 },
> +	{ DE_VIDEO1, 12, DRM_FORMAT_UYVY },
> +	{ DE_VIDEO1, 13, DRM_FORMAT_YUYV },
> +	{ DE_VIDEO1, 14, DRM_FORMAT_NV12 },
> +	{ DE_VIDEO1, 15, DRM_FORMAT_YUV420 },
> +};
> +
> +#define MALIDP_ID(__group, __format) \
> +	((((__group) & 0x7) << 3) | ((__format) & 0x7))
> +
> +#define MALIDP_COMMON_FORMATS \
> +	/*    layers supporting the format,      internal id,      fourcc */ \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 0), DRM_FORMAT_ARGB2101010 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 1), DRM_FORMAT_ABGR2101010 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 2), DRM_FORMAT_RGBA1010102 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 3), DRM_FORMAT_BGRA1010102 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 0), DRM_FORMAT_ARGB8888 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 1), DRM_FORMAT_ABGR8888 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 2), DRM_FORMAT_RGBA8888 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 3), DRM_FORMAT_BGRA8888 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 0), DRM_FORMAT_XRGB8888 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 1), DRM_FORMAT_XBGR8888 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 2), DRM_FORMAT_RGBX8888 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 3), DRM_FORMAT_BGRX8888 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 0), DRM_FORMAT_RGB888 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 1), DRM_FORMAT_BGR888 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 0), DRM_FORMAT_RGBA5551 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 1), DRM_FORMAT_ABGR1555 }, \
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 2), DRM_FORMAT_RGB565 },	\
> +	{ DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 3), DRM_FORMAT_BGR565 },	\
> +	{ DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 2), DRM_FORMAT_YUYV }, \
> +	{ DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 3), DRM_FORMAT_UYVY }, \
> +	{ DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 6), DRM_FORMAT_NV12 }, \
> +	{ DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 7), DRM_FORMAT_YUV420 }
> +
> +static const struct malidp_input_format malidp550_de_formats[] = {
> +	MALIDP_COMMON_FORMATS,
> +};
> +
> +static const struct malidp_input_format malidp650_de_formats[] = {
> +	MALIDP_COMMON_FORMATS,
> +};
> +
> +static const struct malidp_layer malidp500_layers[] = {
> +	{ DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE },
> +	{ DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE },
> +	{ DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE },
> +};
> +
> +static const struct malidp_layer malidp550_layers[] = {
> +	{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE },
> +	{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE },
> +	{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE },
> +	{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE },
> +};
> +
> +#define MALIDP_DE_DEFAULT_PREFETCH_START	5
> +
> +int malidp500_query_hw(struct malidp_hw_device *hwdev)
> +{
> +	u32 conf = malidp_hw_read(hwdev, MALIDP500_CONFIG_ID);
> +	/* bit 4 of the CONFIG_ID register holds the line size multiplier */
> +	u8 ln_size_mult = conf & 0x10 ? 2 : 1;
> +
> +	hwdev->min_line_size = 2;
> +	hwdev->max_line_size = SZ_2K * ln_size_mult;
> +	hwdev->rotation_memory[0] = SZ_1K * 64 * ln_size_mult;
> +	hwdev->rotation_memory[1] = 0; /* no second rotation memory bank */
> +
> +	return 0;
> +}
> +
> +void malidp500_enter_config_mode(struct malidp_hw_device *hwdev)
> +{
> +	u32 status, count = 100;
> +
> +	malidp_hw_setbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
> +	while (count) {
> +		status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
> +		if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
> +			break;
> +		/*
> +		 * entering config mode can take as long as the rendering
> +		 * of a full frame, hence the long sleep here
> +		 */
> +		usleep_range(1000, 10000);
> +		count--;
> +	}
> +	WARN(count == 0, "timeout while entering config mode");
> +}
> +
> +void malidp500_leave_config_mode(struct malidp_hw_device *hwdev)
> +{
> +	u32 status, count = 30;
> +
> +	malidp_hw_clearbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
> +	while (count) {
> +		status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
> +		if ((status & MALIDP500_DC_CONFIG_REQ) == 0)
> +			break;
> +		usleep_range(100, 1000);
> +		count--;
> +	}
> +	WARN(count == 0, "timeout while leaving config mode");
> +}
> +
> +bool malidp500_in_config_mode(struct malidp_hw_device *hwdev)
> +{
> +	u32 status;
> +
> +	status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
> +	if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
> +		return true;
> +
> +	return false;
> +}
> +
> +void malidp500_set_config_valid(struct malidp_hw_device *hwdev)
> +{
> +	malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID);
> +}
> +
> +void malidp500_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
> +{
> +	u32 val = 0;
> +
> +	malidp_hw_clearbits(hwdev, MALIDP500_DC_CLEAR_MASK, MALIDP500_DC_CONTROL);
> +	if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
> +		val |= MALIDP500_HSYNCPOL;
> +	if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
> +		val |= MALIDP500_VSYNCPOL;
> +	val |= MALIDP_DE_DEFAULT_PREFETCH_START;
> +	malidp_hw_setbits(hwdev, val, MALIDP500_DC_CONTROL);
> +
> +	/*
> +	 * Mali-DP500 encodes the background color like this:
> +	 *    - red   @ MALIDP500_BGND_COLOR[12:0]
> +	 *    - green @ MALIDP500_BGND_COLOR[27:16]
> +	 *    - blue  @ (MALIDP500_BGND_COLOR + 4)[12:0]
> +	 */
> +	val = ((MALIDP_BGND_COLOR_G & 0xfff) << 16) |
> +	      (MALIDP_BGND_COLOR_R & 0xfff);
> +	malidp_hw_write(hwdev, val, MALIDP500_BGND_COLOR);
> +	malidp_hw_write(hwdev, MALIDP_BGND_COLOR_B, MALIDP500_BGND_COLOR + 4);
> +
> +	val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) |
> +		MALIDP_DE_H_BACKPORCH(mode->hback_porch);
> +	malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
> +
> +	val = MALIDP500_DE_V_FRONTPORCH(mode->vfront_porch) |
> +		MALIDP_DE_V_BACKPORCH(mode->vback_porch);
> +	malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
> +
> +	val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) |
> +		MALIDP_DE_V_SYNCWIDTH(mode->vsync_len);
> +	malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
> +
> +	val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive);
> +	malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
> +
> +	if (mode->flags & DISPLAY_FLAGS_INTERLACED)
> +		malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
> +	else
> +		malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
> +}
> +
> +int malidp500_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt)
> +{
> +	unsigned int depth;
> +	int bpp;
> +
> +	/* RGB888 or BGR888 can't be rotated */
> +	if ((fmt == DRM_FORMAT_RGB888) || (fmt == DRM_FORMAT_BGR888))
> +		return -EINVAL;
> +
> +	/*
> +	 * Each layer needs enough rotation memory to fit 8 lines
> +	 * worth of pixel data. Required size is then:
> +	 *    size = (rotated_width * bpp * 8 ) / 8;
> +	 */
> +	drm_fb_get_bpp_depth(fmt, &depth, &bpp);
> +
> +	return w * bpp;
> +}
> +
> +static int malidp550_query_hw(struct malidp_hw_device *hwdev)
> +{
> +	u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
> +	u8 ln_size = (conf >> 4) & 0x3, rsize;
> +
> +	hwdev->min_line_size = 2;
> +
> +	switch (ln_size) {
> +	case 0:
> +		hwdev->max_line_size = SZ_2K;
> +		/* two banks of 64KB for rotation memory */
> +		rsize = 64;
> +		break;
> +	case 1:
> +		hwdev->max_line_size = SZ_4K;
> +		/* two banks of 128KB for rotation memory */
> +		rsize = 128;
> +		break;
> +	case 2:
> +		hwdev->max_line_size = 1280;
> +		/* two banks of 40KB for rotation memory */
> +		rsize = 40;
> +		break;
> +	case 3:
> +		/* reserved value */
> +		hwdev->max_line_size = 0;
> +		return -EINVAL;
> +	}
> +
> +	hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
> +	return 0;
> +}
> +
> +void malidp550_enter_config_mode(struct malidp_hw_device *hwdev)
> +{
> +	u32 status, count = 100;
> +
> +	malidp_hw_setbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
> +	while (count) {
> +		status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
> +		if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
> +			break;
> +		/*
> +		 * entering config mode can take as long as the rendering
> +		 * of a full frame, hence the long sleep here
> +		 */
> +		usleep_range(1000, 10000);
> +		count--;
> +	}
> +	WARN(count == 0, "timeout while entering config mode");
> +}
> +
> +void malidp550_leave_config_mode(struct malidp_hw_device *hwdev)
> +{
> +	u32 status, count = 30;
> +
> +	malidp_hw_clearbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
> +	while (count) {
> +		status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
> +		if ((status & MALIDP550_DC_CONFIG_REQ) == 0)
> +			break;
> +		usleep_range(100, 1000);
> +		count--;
> +	}
> +	WARN(count == 0, "timeout while leaving config mode");
> +}
> +
> +bool malidp550_in_config_mode(struct malidp_hw_device *hwdev)
> +{
> +	u32 status;
> +
> +	status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
> +	if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
> +		return true;
> +
> +	return false;
> +}
> +
> +void malidp550_set_config_valid(struct malidp_hw_device *hwdev)
> +{
> +	malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID);
> +}
> +
> +void malidp550_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
> +{
> +	u32 val = MALIDP_DE_DEFAULT_PREFETCH_START;
> +
> +	malidp_hw_write(hwdev, val, MALIDP550_DE_CONTROL);
> +	/*
> +	 * Mali-DP550 and Mali-DP650 encode the background color like this:
> +	 *   - red   @ MALIDP550_DE_BGND_COLOR[23:16]
> +	 *   - green @ MALIDP550_DE_BGND_COLOR[15:8]
> +	 *   - blue  @ MALIDP550_DE_BGND_COLOR[7:0]
> +	 *
> +	 * We need to truncate the least significant 4 bits from the default
> +	 * MALIDP_BGND_COLOR_x values
> +	 */
> +	val = (((MALIDP_BGND_COLOR_R >> 4) & 0xff) << 16) |
> +	      (((MALIDP_BGND_COLOR_G >> 4) & 0xff) << 8) |
> +	      ((MALIDP_BGND_COLOR_B >> 4) & 0xff);
> +	malidp_hw_write(hwdev, val, MALIDP550_DE_BGND_COLOR);
> +
> +	val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) |
> +		MALIDP_DE_H_BACKPORCH(mode->hback_porch);
> +	malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
> +
> +	val = MALIDP550_DE_V_FRONTPORCH(mode->vfront_porch) |
> +		MALIDP_DE_V_BACKPORCH(mode->vback_porch);
> +	malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
> +
> +	val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) |
> +		MALIDP_DE_V_SYNCWIDTH(mode->vsync_len);
> +	if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
> +		val |= MALIDP550_HSYNCPOL;
> +	if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
> +		val |= MALIDP550_VSYNCPOL;
> +	malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
> +
> +	val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive);
> +	malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
> +
> +	if (mode->flags & DISPLAY_FLAGS_INTERLACED)
> +		malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
> +	else
> +		malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
> +}
> +
> +int malidp550_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt)
> +{
> +	u32 bytes_per_col;
> +
> +	/* raw RGB888 or BGR888 can't be rotated */
> +	if ((fmt == DRM_FORMAT_RGB888) || (fmt == DRM_FORMAT_BGR888))
> +		return -EINVAL;
> +
> +	switch (fmt) {
> +	/* 8 lines at 4 bytes per pixel */
> +	case DRM_FORMAT_ARGB2101010:
> +	case DRM_FORMAT_ABGR2101010:
> +	case DRM_FORMAT_RGBA1010102:
> +	case DRM_FORMAT_BGRA1010102:
> +	case DRM_FORMAT_ARGB8888:
> +	case DRM_FORMAT_ABGR8888:
> +	case DRM_FORMAT_RGBA8888:
> +	case DRM_FORMAT_BGRA8888:
> +	case DRM_FORMAT_XRGB8888:
> +	case DRM_FORMAT_XBGR8888:
> +	case DRM_FORMAT_RGBX8888:
> +	case DRM_FORMAT_BGRX8888:
> +	case DRM_FORMAT_RGB888:
> +	case DRM_FORMAT_BGR888:
> +	/* 16 lines at 2 bytes per pixel */
> +	case DRM_FORMAT_RGBA5551:
> +	case DRM_FORMAT_ABGR1555:
> +	case DRM_FORMAT_RGB565:
> +	case DRM_FORMAT_BGR565:
> +	case DRM_FORMAT_UYVY:
> +	case DRM_FORMAT_YUYV:
> +		bytes_per_col = 32;
> +		break;
> +	/* 16 lines at 1.5 bytes per pixel */
> +	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_YUV420:
> +		bytes_per_col = 24;
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	return w * bytes_per_col;
> +}
> +
> +static int malidp650_query_hw(struct malidp_hw_device *hwdev)
> +{
> +	u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
> +	u8 ln_size = (conf >> 4) & 0x3, rsize;
> +
> +	hwdev->min_line_size = 4;
> +
> +	switch (ln_size) {
> +	case 0:
> +	case 2:
> +		/* reserved values */
> +		hwdev->max_line_size = 0;
> +		return -EINVAL;
> +	case 1:
> +		hwdev->max_line_size = SZ_4K;
> +		/* two banks of 128KB for rotation memory */
> +		rsize = 128;
> +		break;
> +	case 3:
> +		hwdev->max_line_size = 2560;
> +		/* two banks of 80KB for rotation memory */
> +		rsize = 80;
> +	}
> +
> +	hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
> +	return 0;
> +}
> +
> +const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = {
> +	[MALIDP_500] = {
> +		.map = {
> +			.se_base = MALIDP500_SE_BASE,
> +			.dc_base = MALIDP500_DC_BASE,
> +			.de_irq_map = {
> +				.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
> +					    MALIDP500_DE_IRQ_AXI_ERR |
> +					    MALIDP500_DE_IRQ_VSYNC |
> +					    MALIDP500_DE_IRQ_GLOBAL,
> +				.vsync_irq = MALIDP500_DE_IRQ_VSYNC,
> +			},
> +			.se_irq_map = {
> +				.irq_mask = MALIDP500_SE_IRQ_CONF_MODE,
> +				.vsync_irq = 0,
> +			},
> +			.dc_irq_map = {
> +				.irq_mask = MALIDP500_DE_IRQ_CONF_VALID,
> +				.vsync_irq = MALIDP500_DE_IRQ_CONF_VALID,
> +			},
> +			.layers = malidp500_layers,
> +			.n_layers = ARRAY_SIZE(malidp500_layers),
> +			.input_formats = malidp500_de_formats,
> +			.n_input_formats = ARRAY_SIZE(malidp500_de_formats),
> +			.out_depth_base = MALIDP500_OUTPUT_DEPTH,
> +			.features = 0,	/* no CLEARIRQ register */
> +		},
> +		.query_hw = malidp500_query_hw,
> +		.enter_config_mode = malidp500_enter_config_mode,
> +		.leave_config_mode = malidp500_leave_config_mode,
> +		.in_config_mode = malidp500_in_config_mode,
> +		.set_config_valid = malidp500_set_config_valid,
> +		.modeset = malidp500_modeset,
> +		.rotmem_required = malidp500_rotmem_required,
> +	},
> +	[MALIDP_550] = {
> +		.map = {
> +			.se_base = MALIDP550_SE_BASE,
> +			.dc_base = MALIDP550_DC_BASE,
> +			.de_irq_map = {
> +				.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
> +					    MALIDP550_DE_IRQ_VSYNC,
> +				.vsync_irq = MALIDP550_DE_IRQ_VSYNC,
> +			},
> +			.se_irq_map = {
> +				.irq_mask = MALIDP550_SE_IRQ_EOW |
> +					    MALIDP550_SE_IRQ_AXI_ERR,
> +			},
> +			.dc_irq_map = {
> +				.irq_mask = MALIDP550_DC_IRQ_CONF_VALID,
> +				.vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
> +			},
> +			.layers = malidp550_layers,
> +			.n_layers = ARRAY_SIZE(malidp550_layers),
> +			.input_formats = malidp550_de_formats,
> +			.n_input_formats = ARRAY_SIZE(malidp550_de_formats),
> +			.out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
> +			.features = MALIDP_REGMAP_HAS_CLEARIRQ,
> +		},
> +		.query_hw = malidp550_query_hw,
> +		.enter_config_mode = malidp550_enter_config_mode,
> +		.leave_config_mode = malidp550_leave_config_mode,
> +		.in_config_mode = malidp550_in_config_mode,
> +		.set_config_valid = malidp550_set_config_valid,
> +		.modeset = malidp550_modeset,
> +		.rotmem_required = malidp550_rotmem_required,
> +	},
> +	[MALIDP_650] = {
> +		.map = {
> +			.se_base = MALIDP550_SE_BASE,
> +			.dc_base = MALIDP550_DC_BASE,
> +			.de_irq_map = {
> +				.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
> +					    MALIDP650_DE_IRQ_DRIFT |
> +					    MALIDP550_DE_IRQ_VSYNC,
> +				.vsync_irq = MALIDP550_DE_IRQ_VSYNC,
> +			},
> +			.se_irq_map = {
> +				.irq_mask = MALIDP550_SE_IRQ_EOW |
> +					    MALIDP550_SE_IRQ_AXI_ERR,
> +			},
> +			.dc_irq_map = {
> +				.irq_mask = MALIDP550_DC_IRQ_CONF_VALID,
> +				.vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
> +			},
> +			.layers = malidp550_layers,
> +			.n_layers = ARRAY_SIZE(malidp550_layers),
> +			.input_formats = malidp650_de_formats,
> +			.n_input_formats = ARRAY_SIZE(malidp650_de_formats),
> +			.out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
> +			.features = MALIDP_REGMAP_HAS_CLEARIRQ,
> +		},
> +		.query_hw = malidp650_query_hw,
> +		.enter_config_mode = malidp550_enter_config_mode,
> +		.leave_config_mode = malidp550_leave_config_mode,
> +		.in_config_mode = malidp550_in_config_mode,
> +		.set_config_valid = malidp550_set_config_valid,
> +		.modeset = malidp550_modeset,
> +		.rotmem_required = malidp550_rotmem_required,
> +	},
> +};
> +
> +u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
> +			   u8 layer_id, u32 format)
> +{
> +	unsigned int i;
> +
> +	for (i = 0; i < map->n_input_formats; i++) {
> +		if (((map->input_formats[i].layer & layer_id) == layer_id) &&
> +		    (map->input_formats[i].format == format))
> +			return map->input_formats[i].id;
> +	}
> +
> +	return (u8)-1;
> +}
> +
> +
> +u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg)
> +{
> +	u32 value = readl(hwdev->regs + reg);
> +	return value;
> +}
> +
> +void malidp_hw_write(struct malidp_hw_device *hwdev, u32 value, u32 reg)
> +{
> +	writel(value, hwdev->regs + reg);
> +}
> +
> +void malidp_hw_setbits(struct malidp_hw_device *hwdev, u32 mask, u32 reg)
> +{
> +	u32 data = malidp_hw_read(hwdev, reg);
> +
> +	data |= mask;
> +	malidp_hw_write(hwdev, data, reg);
> +}
> +
> +void malidp_hw_clearbits(struct malidp_hw_device *hwdev, u32 mask, u32 reg)
> +{
> +	u32 data = malidp_hw_read(hwdev, reg);
> +
> +	data &= ~mask;
> +	malidp_hw_write(hwdev, data, reg);
> +}
> +
> +void malidp_hw_clear_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq)
> +{
> +	u32 base = 0;
> +
> +	switch (block) {
> +	case MALIDP_DE_BLOCK:
> +		base = 0;
> +		break;
> +	case MALIDP_SE_BLOCK:
> +		base = hwdev->map.se_base;
> +		break;
> +	case MALIDP_DC_BLOCK:
> +		base = hwdev->map.dc_base;
> +		break;
> +	}
> +
> +	if (hwdev->map.features & MALIDP_REGMAP_HAS_CLEARIRQ)
> +		malidp_hw_write(hwdev, irq, base + MALIDP_REG_CLEARIRQ);
> +	else
> +		malidp_hw_write(hwdev, irq, base + MALIDP_REG_STATUS);
> +}
> +
> +void malidp_hw_disable_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq)
> +{
> +	u32 base = 0;
> +
> +	switch (block) {
> +	case MALIDP_DE_BLOCK:
> +		base = 0;
> +		break;
> +	case MALIDP_SE_BLOCK:
> +		base = hwdev->map.se_base;
> +		break;
> +	case MALIDP_DC_BLOCK:
> +		base = hwdev->map.dc_base;
> +		break;
> +	}
> +
> +	malidp_hw_clearbits(hwdev, irq, base + MALIDP_REG_MASKIRQ);
> +}
> +
> +void malidp_hw_enable_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq)
> +{
> +	u32 base = 0;
> +
> +	switch (block) {
> +	case MALIDP_DE_BLOCK:
> +		base = 0;
> +		break;
> +	case MALIDP_SE_BLOCK:
> +		base = hwdev->map.se_base;
> +		break;
> +	case MALIDP_DC_BLOCK:
> +		base = hwdev->map.dc_base;
> +		break;
> +	}
> +
> +	malidp_hw_setbits(hwdev, irq, base + MALIDP_REG_MASKIRQ);
> +}
> +
> +static irqreturn_t malidp_de_irq(int irq, void *arg)
> +{
> +	struct drm_device *drm = arg;
> +	struct malidp_drm *malidp = drm->dev_private;
> +	struct malidp_hw_device *hwdev;
> +	const struct malidp_irq_map *de;
> +	u32 status, mask, dc_status;
> +	irqreturn_t ret = IRQ_NONE;
> +
> +	if (!drm->dev_private)
> +		return IRQ_HANDLED;
> +
> +	hwdev = malidp->dev;
> +	de = &hwdev->map.de_irq_map;
> +
> +	/* first handle the config valid IRQ */
> +	dc_status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
> +	if (dc_status & hwdev->map.dc_irq_map.vsync_irq) {
> +		/* we have a page flip event */
> +		atomic_set(&malidp->config_valid, 1);
> +		malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status);
> +		ret = IRQ_WAKE_THREAD;
> +	}
> +
> +	status = malidp_hw_read(hwdev, MALIDP_REG_STATUS);
> +	if (!(status & de->irq_mask))
> +		return ret;
> +
> +	mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ);
> +	status &= mask;
> +	if (status & de->vsync_irq)
> +		drm_crtc_handle_vblank(&malidp->crtc);
> +
> +	malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, status);
> +
> +	return (ret == IRQ_NONE) ? IRQ_HANDLED : ret;
> +}
> +
> +static irqreturn_t malidp_de_irq_thread_handler(int irq, void *arg)
> +{
> +	struct drm_device *drm = arg;
> +	struct malidp_drm *malidp = drm->dev_private;
> +
> +	wake_up(&malidp->wq);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +int malidp_de_irq_init(struct drm_device *drm, int irq)
> +{
> +	struct malidp_drm *malidp = drm->dev_private;
> +	struct malidp_hw_device *hwdev = malidp->dev;
> +	int ret;
> +
> +	/* ensure interrupts are disabled */
> +	malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
> +	malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
> +	malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
> +	malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
> +
> +	ret = devm_request_threaded_irq(drm->dev, irq, malidp_de_irq,
> +					malidp_de_irq_thread_handler,
> +					IRQF_SHARED, "malidp-de", drm);
> +	if (ret < 0) {
> +		DRM_ERROR("failed to install DE IRQ handler\n");
> +		return ret;
> +	}
> +
> +	/* first enable the DC block IRQs */
> +	malidp_hw_enable_irq(hwdev, MALIDP_DC_BLOCK,
> +			     hwdev->map.dc_irq_map.irq_mask);
> +
> +	/* now enable the DE block IRQs */
> +	malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
> +			     hwdev->map.de_irq_map.irq_mask);
> +
> +	return 0;
> +}
> +
> +void malidp_de_irq_cleanup(struct drm_device *drm)
> +{
> +	struct malidp_drm *malidp = drm->dev_private;
> +	struct malidp_hw_device *hwdev = malidp->dev;
> +
> +	malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
> +			      hwdev->map.de_irq_map.irq_mask);
> +	malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK,
> +			      hwdev->map.dc_irq_map.irq_mask);
> +}
> +
> +static irqreturn_t malidp_se_irq(int irq, void *arg)
> +{
> +	struct drm_device *drm = arg;
> +	struct malidp_drm *malidp = drm->dev_private;
> +	struct malidp_hw_device *hwdev = malidp->dev;
> +	u32 status, mask;
> +
> +	status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS);
> +	if (!(status & hwdev->map.se_irq_map.irq_mask))
> +		return IRQ_NONE;
> +
> +	mask = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_MASKIRQ);
> +	status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS);
> +	status &= mask;
> +	/* ToDo: status decoding and firing up of VSYNC and page flip events */
> +
> +	malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, status);
> +	/* return IRQ_WAKE_THREAD; */
> +	return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t malidp_se_irq_thread_handler(int irq, void *arg)
> +{
> +	return IRQ_HANDLED;
> +}
> +
> +int malidp_se_irq_init(struct drm_device *drm, int irq)
> +{
> +	struct malidp_drm *malidp = drm->dev_private;
> +	struct malidp_hw_device *hwdev = malidp->dev;
> +	int ret;
> +
> +	/* ensure interrupts are disabled */
> +	malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
> +	malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
> +
> +	ret = devm_request_threaded_irq(drm->dev, irq, malidp_se_irq,
> +					malidp_se_irq_thread_handler,
> +					IRQF_SHARED, "malidp-se", drm);
> +	if (ret < 0) {
> +		DRM_ERROR("failed to install SE IRQ handler\n");
> +		return ret;
> +	}
> +
> +	malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK,
> +			     hwdev->map.se_irq_map.irq_mask);
> +
> +	return 0;
> +}
> +
> +void malidp_se_irq_cleanup(struct drm_device *drm)
> +{
> +	struct malidp_drm *malidp = drm->dev_private;
> +	struct malidp_hw_device *hwdev = malidp->dev;
> +
> +	malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK,
> +			      hwdev->map.se_irq_map.irq_mask);
> +}
> diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h
> new file mode 100644
> index 0000000..fab1fe7
> --- /dev/null
> +++ b/drivers/gpu/drm/arm/malidp_hw.h
> @@ -0,0 +1,189 @@
> +/*
> + *
> + * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved.
> + *
> + * This program is free software and is provided to you under the terms of the
> + * GNU General Public License version 2 as published by the Free Software
> + * Foundation, and any use by you of this program is subject to the terms
> + * of such GNU licence.
> + *
> + * ARM Mali DP hardware manipulation routines.
> + */
> +
> +#ifndef __MALIDP_HW_H__
> +#define __MALIDP_HW_H__
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/bitops.h>
> +
> +struct videomode;
> +struct clk;
> +
> +/* Mali DP IP blocks */
> +enum {
> +	MALIDP_DE_BLOCK = 0,
> +	MALIDP_SE_BLOCK,
> +	MALIDP_DC_BLOCK
> +};
> +
> +/* Mali DP layer IDs */
> +enum {
> +	DE_VIDEO1 = BIT(0),
> +	DE_GRAPHICS1 = BIT(1),
> +	DE_GRAPHICS2 = BIT(2), /* used only in DP500 */
> +	DE_VIDEO2 = BIT(3),
> +	DE_SMART = BIT(4),
> +};
> +
> +struct malidp_input_format {
> +	u8 layer;		/* bitmask of layers supporting it */
> +	u8 id;			/* used internally */
> +	u32 format;		/* DRM fourcc */
> +};
> +
> +/*
> + * hide the differences between register maps
> + * by using a common structure to hold the
> + * base register offsets
> + */
> +
> +struct malidp_irq_map {
> +	u32 irq_mask;		/* mask of IRQs that can be enabled in the block */
> +	u32 vsync_irq;		/* IRQ bit used for signaling during VSYNC */
> +};
> +
> +struct malidp_layer {
> +	u8 id;			/* layer ID */
> +	u16 base;		/* address offset for the register bank */
> +	u16 ptr;		/* address offset for the pointer register */
> +};
> +
> +/* regmap features */
> +#define MALIDP_REGMAP_HAS_CLEARIRQ	(1 << 0)
> +
> +struct malidp_hw_regmap {
> +	/* address offset of the DE register bank */
> +	/* is always 0x0000 */
> +	/* address offset of the SE registers bank */
> +	const u16 se_base;
> +	/* address offset of the DC registers bank */
> +	const u16 dc_base;
> +
> +	const struct malidp_irq_map de_irq_map;
> +	const struct malidp_irq_map se_irq_map;
> +	const struct malidp_irq_map dc_irq_map;
> +
> +	/* list of supported layers */
> +	const struct malidp_layer *layers;
> +	const u8 n_layers;
> +
> +	/* list of supported input formats for each layer */
> +	const struct malidp_input_format *input_formats;
> +	const u8 n_input_formats;
> +
> +	/* address offset for the output depth register */
> +	const u16 out_depth_base;
> +
> +	/* bitmap with register map features */
> +	const u8 features;
> +};
> +
> +struct malidp_hw_device {
> +	const struct malidp_hw_regmap map;
> +	void __iomem *regs;
> +
> +	/* APB clock */
> +	struct clk *pclk;
> +	/* AXI clock */
> +	struct clk *aclk;
> +	/* main clock for display core */
> +	struct clk *mclk;
> +	/* pixel clock for display core */
> +	struct clk *pxlclk;
> +
> +	/*
> +	 * Validate the driver instance against the hardware bits
> +	 */
> +	int (*query_hw)(struct malidp_hw_device *hwdev);
> +
> +	/*
> +	 * Set the hardware into config mode, ready to accept mode changes
> +	 */
> +	void (*enter_config_mode)(struct malidp_hw_device *hwdev);
> +
> +	/*
> +	 * Tell hardware to exit configuration mode
> +	 */
> +	void (*leave_config_mode)(struct malidp_hw_device *hwdev);
> +
> +	/*
> +	 * Query if hardware is in configuration mode
> +	 */
> +	bool (*in_config_mode)(struct malidp_hw_device *hwdev);
> +
> +	/*
> +	 * Set configuration valid flag for hardware parameters that can
> +	 * be changed outside the configuration mode. Hardware will use
> +	 * the new settings when config valid is set after the end of the
> +	 * current buffer scanout
> +	 */
> +	void (*set_config_valid)(struct malidp_hw_device *hwdev);
> +
> +	/*
> +	 * Set a new mode in hardware. Requires the hardware to be in
> +	 * configuration mode before this function is called.
> +	 */
> +	void (*modeset)(struct malidp_hw_device *hwdev, struct videomode *m);
> +
> +	/*
> +	 * Calculate the required rotation memory given the active area
> +	 * and the buffer format.
> +	 */
> +	int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt);
> +
> +	u8 features;
> +
> +	u8 min_line_size;
> +	u16 max_line_size;
> +
> +	/* size of memory used for rotating layers, up to two banks available */
> +	u32 rotation_memory[2];
> +};
> +
> +/* Supported variants of the hardware */
> +enum {
> +	MALIDP_500 = 0,
> +	MALIDP_550,
> +	MALIDP_650,
> +	/* keep the next entry last */
> +	MALIDP_MAX_DEVICES
> +};
> +
> +extern const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES];
> +
> +u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg);
> +void malidp_hw_write(struct malidp_hw_device *hwdev, u32 value, u32 reg);
> +void malidp_hw_setbits(struct malidp_hw_device *hwdev, u32 mask, u32 reg);
> +void malidp_hw_clearbits(struct malidp_hw_device *hwdev, u32 mask, u32 reg);
> +void malidp_hw_clear_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq);
> +void malidp_hw_disable_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq);
> +void malidp_hw_enable_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq);
> +
> +int malidp_de_irq_init(struct drm_device *drm, int irq);
> +int malidp_se_irq_init(struct drm_device *drm, int irq);
> +void malidp_de_irq_cleanup(struct drm_device *drm);
> +void malidp_se_irq_cleanup(struct drm_device *drm);
> +
> +u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
> +			   u8 layer_id, u32 format);
> +
> +/*
> + * background color components are defined as 12bits values,
> + * they will be shifted right when stored on hardware that
> + * supports only 8bits per channel
> + */
> +#define MALIDP_BGND_COLOR_R		0x000
> +#define MALIDP_BGND_COLOR_G		0x000
> +#define MALIDP_BGND_COLOR_B		0x000
> +
> +#endif  /* __MALIDP_HW_H__ */
> diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c
> new file mode 100644
> index 0000000..665aa0e
> --- /dev/null
> +++ b/drivers/gpu/drm/arm/malidp_planes.c
> @@ -0,0 +1,337 @@
> +/*
> + * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
> + * Author: Liviu Dudau <Liviu.Dudau@arm.com>
> + *
> + * This program is free software and is provided to you under the terms of the
> + * GNU General Public License version 2 as published by the Free Software
> + * Foundation, and any use by you of this program is subject to the terms
> + * of such GNU licence.
> + *
> + * ARM Mali DP plane manipulation routines.
> + */
> +
> +#include <drm/drmP.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_fb_cma_helper.h>
> +#include <drm/drm_gem_cma_helper.h>
> +#include <drm/drm_plane_helper.h>
> +
> +#include "malidp_hw.h"
> +#include "malidp_drv.h"
> +
> +/* Layer specific register offsets */
> +#define MALIDP_LAYER_FORMAT		0x000
> +#define MALIDP_LAYER_CONTROL		0x004
> +#define   LAYER_ENABLE			(1 << 0)
> +#define   LAYER_ROT_OFFSET		8
> +#define   LAYER_H_FLIP			(1 << 10)
> +#define   LAYER_V_FLIP			(1 << 11)
> +#define   LAYER_ROT_MASK		(0xf << 8)
> +#define MALIDP_LAYER_SIZE		0x00c
> +#define   LAYER_H_VAL(x)		(((x) & 0x1fff) << 0)
> +#define   LAYER_V_VAL(x)		(((x) & 0x1fff) << 16)
> +#define MALIDP_LAYER_COMP_SIZE		0x010
> +#define MALIDP_LAYER_OFFSET		0x014
> +#define MALIDP_LAYER_STRIDE		0x018
> +
> +static void malidp_de_plane_destroy(struct drm_plane *plane)
> +{
> +	struct malidp_plane *mp = to_malidp_plane(plane);
> +
> +	if (mp->base.fb)
> +		drm_framebuffer_unreference(mp->base.fb);
> +
> +	drm_plane_helper_disable(plane);
> +	drm_plane_cleanup(plane);
> +	devm_kfree(plane->dev->dev, mp);
> +}
> +
> +static int malidp_de_atomic_update_plane(struct drm_plane *plane,
> +					 struct drm_crtc *crtc,
> +					 struct drm_framebuffer *fb,
> +					 int crtc_x, int crtc_y,
> +					 unsigned int crtc_w,
> +					 unsigned int crtc_h,
> +					 uint32_t src_x, uint32_t src_y,
> +					 uint32_t src_w, uint32_t src_h)
> +{
> +	return drm_atomic_helper_update_plane(plane, crtc, fb, crtc_x, crtc_y,
> +					      crtc_w, crtc_h, src_x, src_y,
> +					      src_w, src_h);
> +}
> +
> +static int malidp_de_plane_atomic_set_property(struct drm_plane *plane,
> +					       struct drm_plane_state *state,
> +					       struct drm_property *property,
> +					       uint64_t val)
> +{
> +	return drm_atomic_helper_plane_set_property(plane, property, val);
> +}
> +
> +static const struct drm_plane_funcs malidp_de_plane_funcs = {
> +	.update_plane = malidp_de_atomic_update_plane,
> +	.disable_plane = drm_atomic_helper_disable_plane,
> +	.destroy = malidp_de_plane_destroy,
> +	.reset = drm_atomic_helper_plane_reset,
> +	.set_property = drm_atomic_helper_plane_set_property,
> +	.atomic_set_property = malidp_de_plane_atomic_set_property,
> +	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
> +	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
> +};
> +
> +static int malidp_de_plane_check(struct drm_plane *plane,
> +				 struct drm_plane_state *state)
> +{
> +	struct malidp_plane *mp = to_malidp_plane(plane);
> +	u32 src_w, src_h;
> +
> +	if (!state->crtc || !state->fb)
> +		return 0;
> +
> +	src_w = state->src_w >> 16;
> +	src_h = state->src_h >> 16;
> +
> +	if ((state->crtc_w > mp->hwdev->max_line_size) ||
> +	    (state->crtc_h > mp->hwdev->max_line_size) ||
> +	    (state->crtc_w < mp->hwdev->min_line_size) ||
> +	    (state->crtc_h < mp->hwdev->min_line_size) ||
> +	    (state->crtc_w != src_w) || (state->crtc_h != src_h))
> +		return -EINVAL;
> +
> +	/* packed RGB888 / BGR888 can't be rotated or flipped */
> +	if (state->rotation != BIT(DRM_ROTATE_0) &&
> +	    (state->fb->pixel_format == DRM_FORMAT_RGB888 ||
> +	     state->fb->pixel_format == DRM_FORMAT_BGR888))
> +		return -EINVAL;
> +
> +	mp->rotmem_size = 0;
> +	if (state->rotation & MALIDP_ROTATED_MASK) {
> +		int val;
> +
> +		val = mp->hwdev->rotmem_required(mp->hwdev, state->crtc_h,
> +						 state->crtc_w,
> +						 state->fb->pixel_format);
> +		if (val < 0)
> +			return val;
> +
> +		mp->rotmem_size = val;
> +	}
> +
> +	return 0;
> +}
> +
> +static void malidp_de_plane_update(struct drm_plane *plane,
> +				   struct drm_plane_state *old_state)
> +{
> +	struct drm_gem_cma_object *obj;
> +	struct malidp_plane *mp;
> +	const struct malidp_hw_regmap *map;
> +	u8 format_id;
> +	u16 ptr;
> +	u32 format, src_w, src_h, dest_w, dest_h, val = 0;
> +	int num_planes, i;
> +
> +	mp = to_malidp_plane(plane);
> +
> +#ifdef MALIDP_ENABLE_BGND_COLOR_AS_PRIMARY_PLANE
> +	/* skip the primary plane, it is using the background color */
> +	if (!mp->layer || !mp->layer->id)
> +		return;
> +#endif
> +
> +	map = &mp->hwdev->map;
> +	format = plane->state->fb->pixel_format;
> +	format_id = malidp_hw_get_format_id(map, mp->layer->id, format);
> +	if (format_id == (u8)-1)
> +		return;
> +
> +	num_planes = drm_format_num_planes(format);
> +
> +	/* convert src values from Q16 fixed point to integer */
> +	src_w = plane->state->src_w >> 16;
> +	src_h = plane->state->src_h >> 16;
> +	if (plane->state->rotation & MALIDP_ROTATED_MASK) {
> +		dest_w = plane->state->crtc_h;
> +		dest_h = plane->state->crtc_w;
> +	} else {
> +		dest_w = plane->state->crtc_w;
> +		dest_h = plane->state->crtc_h;
> +	}
> +
> +	malidp_hw_write(mp->hwdev, format_id, mp->layer->base);
> +
> +	for (i = 0; i < num_planes; i++) {
> +		/* calculate the offset for the layer's plane registers */
> +		ptr = mp->layer->ptr + (i << 4);
> +
> +		obj = drm_fb_cma_get_gem_obj(plane->state->fb, i);
> +		malidp_hw_write(mp->hwdev, lower_32_bits(obj->paddr), ptr);
> +		malidp_hw_write(mp->hwdev, upper_32_bits(obj->paddr), ptr + 4);
> +		malidp_hw_write(mp->hwdev, plane->state->fb->pitches[i],
> +				mp->layer->base + MALIDP_LAYER_STRIDE);
> +	}
> +
> +	malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
> +			mp->layer->base + MALIDP_LAYER_SIZE);
> +
> +	malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h),
> +			mp->layer->base + MALIDP_LAYER_COMP_SIZE);
> +
> +	malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) |
> +			LAYER_V_VAL(plane->state->crtc_y),
> +			mp->layer->base + MALIDP_LAYER_OFFSET);
> +
> +	/* first clear the rotation bits in the register */
> +	malidp_hw_clearbits(mp->hwdev, LAYER_ROT_MASK,
> +			    mp->layer->base + MALIDP_LAYER_CONTROL);
> +
> +	/* setup the rotation and axis flip bits */
> +	if (plane->state->rotation & DRM_ROTATE_MASK)
> +		val = ilog2(plane->state->rotation & DRM_ROTATE_MASK) << LAYER_ROT_OFFSET;
> +	if (plane->state->rotation & BIT(DRM_REFLECT_X))
> +		val |= LAYER_V_FLIP;
> +	if (plane->state->rotation & BIT(DRM_REFLECT_Y))
> +		val |= LAYER_H_FLIP;
> +
> +	/* set the 'enable layer' bit */
> +	val |= LAYER_ENABLE;
> +
> +	malidp_hw_setbits(mp->hwdev, val,
> +			  mp->layer->base + MALIDP_LAYER_CONTROL);
> +}
> +
> +static void malidp_de_plane_disable(struct drm_plane *plane,
> +				    struct drm_plane_state *state)
> +{
> +	struct malidp_plane *mp = to_malidp_plane(plane);
> +
> +	malidp_hw_clearbits(mp->hwdev, LAYER_ENABLE,
> +			    mp->layer->base + MALIDP_LAYER_CONTROL);
> +}
> +
> +static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = {
> +	.atomic_check = malidp_de_plane_check,
> +	.atomic_update = malidp_de_plane_update,
> +	.atomic_disable = malidp_de_plane_disable,
> +};
> +
> +#ifdef MALIDP_ENABLE_BGND_COLOR_AS_PRIMARY_PLANE
> +static const uint32_t safe_modeset_formats[] = {
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_ARGB8888,
> +};
> +
> +static int malidp_de_create_primary_plane(struct drm_device *drm)
> +{
> +	struct malidp_drm *malidp = drm->dev_private;
> +	struct malidp_plane *plane;
> +	int ret;
> +
> +	plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
> +	if (!plane)
> +		return -ENOMEM;
> +
> +	ret = drm_universal_plane_init(drm, &plane->base, 0,
> +				       &malidp_de_plane_funcs,
> +				       safe_modeset_formats,
> +				       ARRAY_SIZE(safe_modeset_formats),
> +				       DRM_PLANE_TYPE_PRIMARY, NULL);
> +	if (ret)
> +		return ret;
> +
> +	drm_plane_helper_add(&plane->base, &malidp_de_plane_helper_funcs);
> +	plane->hwdev = malidp->dev;
> +
> +	return 0;
> +}
> +#endif
> +
> +int malidp_de_planes_init(struct drm_device *drm)
> +{
> +	struct malidp_drm *malidp = drm->dev_private;
> +	const struct malidp_hw_regmap *map = &malidp->dev->map;
> +	struct malidp_plane *plane = NULL;
> +	enum drm_plane_type plane_type;
> +	unsigned long crtcs = 1 << drm->mode_config.num_crtc;
> +	u32 *formats;
> +	int ret, i, j, n;
> +
> +#ifdef MALIDP_ENABLE_BGND_COLOR_AS_PRIMARY_PLANE
> +	ret = malidp_de_create_primary_plane(drm);
> +	if (ret)
> +		return ret;
> +	plane_type = DRM_PLANE_TYPE_OVERLAY;
> +#endif
> +
> +	formats = kcalloc(map->n_input_formats, sizeof(*formats), GFP_KERNEL);
> +	if (!formats) {
> +		ret = -ENOMEM;
> +		goto cleanup;
> +	}
> +
> +	for (i = 0; i < map->n_layers; i++) {
> +		u8 id = map->layers[i].id;
> +
> +		plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
> +		if (!plane) {
> +			ret = -ENOMEM;
> +			goto cleanup;
> +		}
> +
> +		/* build the list of DRM supported formats based on the map */
> +		for (n = 0, j = 0;  j < map->n_input_formats; j++) {
> +			if ((map->input_formats[j].layer & id) == id)
> +				formats[n++] = map->input_formats[j].format;
> +		}
> +
> +#ifndef MALIDP_ENABLE_BGND_COLOR_AS_PRIMARY_PLANE
> +		plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
> +					DRM_PLANE_TYPE_OVERLAY;
> +#endif
> +		ret = drm_universal_plane_init(drm, &plane->base, crtcs,
> +					       &malidp_de_plane_funcs, formats,
> +					       n, plane_type, NULL);
> +		if (ret < 0)
> +			goto cleanup;
> +
> +		if (!drm->mode_config.rotation_property) {
> +			unsigned long flags = BIT(DRM_ROTATE_0) |
> +					      BIT(DRM_ROTATE_90) |
> +					      BIT(DRM_ROTATE_180) |
> +					      BIT(DRM_ROTATE_270) |
> +					      BIT(DRM_REFLECT_X) |
> +					      BIT(DRM_REFLECT_Y);
> +			drm->mode_config.rotation_property =
> +				drm_mode_create_rotation_property(drm, flags);
> +		}
> +		/* SMART layer can't be rotated */
> +		if (drm->mode_config.rotation_property && (id != DE_SMART))
> +			drm_object_attach_property(&plane->base.base,
> +						   drm->mode_config.rotation_property,
> +						   BIT(DRM_ROTATE_0));
> +
> +		drm_plane_helper_add(&plane->base,
> +				     &malidp_de_plane_helper_funcs);
> +		plane->hwdev = malidp->dev;
> +		plane->layer = &map->layers[i];
> +	}
> +
> +	kfree(formats);
> +
> +	return 0;
> +
> +cleanup:
> +	malidp_de_planes_destroy(drm);
> +	kfree(formats);
> +
> +	return ret;
> +}
> +
> +void malidp_de_planes_destroy(struct drm_device *drm)
> +{
> +	struct drm_plane *p, *pt;
> +
> +	list_for_each_entry_safe(p, pt, &drm->mode_config.plane_list, head) {
> +		drm_plane_cleanup(p);
> +	}
> +}
> diff --git a/drivers/gpu/drm/arm/malidp_regs.h b/drivers/gpu/drm/arm/malidp_regs.h
> new file mode 100644
> index 0000000..73fecb3
> --- /dev/null
> +++ b/drivers/gpu/drm/arm/malidp_regs.h
> @@ -0,0 +1,172 @@
> +/*
> + * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
> + * Author: Liviu Dudau <Liviu.Dudau@arm.com>
> + *
> + * This program is free software and is provided to you under the terms of the
> + * GNU General Public License version 2 as published by the Free Software
> + * Foundation, and any use by you of this program is subject to the terms
> + * of such GNU licence.
> + *
> + * ARM Mali DP500/DP550/DP650 registers definition.
> + */
> +
> +#ifndef __MALIDP_REGS_H__
> +#define __MALIDP_REGS_H__
> +
> +/*
> + * abbreviations used:
> + *    - DC - display core (general settings)
> + *    - DE - display engine
> + *    - SE - scaling engine
> + */
> +
> +/* interrupt bit masks */
> +#define MALIDP_DE_IRQ_UNDERRUN			(1 << 0)
> +
> +#define MALIDP500_DE_IRQ_AXI_ERR		(1 << 4)
> +#define MALIDP500_DE_IRQ_VSYNC			(1 << 5)
> +#define MALIDP500_DE_IRQ_PROG_LINE		(1 << 6)
> +#define MALIDP500_DE_IRQ_SATURATION		(1 << 7)
> +#define MALIDP500_DE_IRQ_CONF_VALID		(1 << 8)
> +#define MALIDP500_DE_IRQ_CONF_MODE		(1 << 11)
> +#define MALIDP500_DE_IRQ_CONF_ACTIVE		(1 << 17)
> +#define MALIDP500_DE_IRQ_PM_ACTIVE		(1 << 18)
> +#define MALIDP500_DE_IRQ_TESTMODE_ACTIVE	(1 << 19)
> +#define MALIDP500_DE_IRQ_FORCE_BLNK_ACTIVE	(1 << 24)
> +#define MALIDP500_DE_IRQ_AXI_BUSY		(1 << 28)
> +#define MALIDP500_DE_IRQ_GLOBAL			(1 << 31)
> +#define MALIDP500_SE_IRQ_CONF_MODE		(1 << 0)
> +#define MALIDP500_SE_IRQ_CONF_VALID		(1 << 4)
> +#define MALIDP500_SE_IRQ_INIT_BUSY		(1 << 5)
> +#define MALIDP500_SE_IRQ_AXI_ERROR		(1 << 8)
> +#define MALIDP500_SE_IRQ_OVERRUN		(1 << 9)
> +#define MALIDP500_SE_IRQ_PROG_LINE1		(1 << 12)
> +#define MALIDP500_SE_IRQ_PROG_LINE2		(1 << 13)
> +#define MALIDP500_SE_IRQ_CONF_ACTIVE		(1 << 17)
> +#define MALIDP500_SE_IRQ_PM_ACTIVE		(1 << 18)
> +#define MALIDP500_SE_IRQ_AXI_BUSY		(1 << 28)
> +#define MALIDP500_SE_IRQ_GLOBAL			(1 << 31)
> +
> +#define MALIDP550_DE_IRQ_SATURATION		(1 << 8)
> +#define MALIDP550_DE_IRQ_VSYNC			(1 << 12)
> +#define MALIDP550_DE_IRQ_PROG_LINE		(1 << 13)
> +#define MALIDP550_DE_IRQ_AXI_ERR		(1 << 16)
> +#define MALIDP550_SE_IRQ_EOW			(1 << 0)
> +#define MALIDP550_SE_IRQ_AXI_ERR		(1 << 16)
> +#define MALIDP550_DC_IRQ_CONF_VALID		(1 << 0)
> +#define MALIDP550_DC_IRQ_CONF_MODE		(1 << 4)
> +#define MALIDP550_DC_IRQ_CONF_ACTIVE		(1 << 16)
> +#define MALIDP550_DC_IRQ_DE			(1 << 20)
> +#define MALIDP550_DC_IRQ_SE			(1 << 24)
> +
> +#define MALIDP650_DE_IRQ_DRIFT			(1 << 4)
> +
> +/* bit masks that are common between products */
> +#define   MALIDP_CFG_VALID		(1 << 0)
> +#define   MALIDP_DISP_FUNC_ILACED	(1 << 8)
> +
> +/* register offsets for IRQ management */
> +#define MALIDP_REG_STATUS		0x00000
> +#define MALIDP_REG_SETIRQ		0x00004
> +#define MALIDP_REG_MASKIRQ		0x00008
> +#define MALIDP_REG_CLEARIRQ		0x0000c
> +
> +/* register offsets */
> +#define MALIDP_DE_CORE_ID		0x00018
> +#define MALIDP_DE_DISPLAY_FUNC		0x00020
> +
> +/* these offsets are relative to MALIDP5x0_TIMINGS_BASE */
> +#define MALIDP_DE_H_TIMINGS		0x0
> +#define MALIDP_DE_V_TIMINGS		0x4
> +#define MALIDP_DE_SYNC_WIDTH		0x8
> +#define MALIDP_DE_HV_ACTIVE		0xc
> +
> +/* macros to set values into registers */
> +#define MALIDP_DE_H_FRONTPORCH(x)	(((x) & 0xfff) << 0)
> +#define MALIDP_DE_H_BACKPORCH(x)	(((x) & 0x3ff) << 16)
> +#define MALIDP500_DE_V_FRONTPORCH(x)	(((x) & 0xff) << 0)
> +#define MALIDP550_DE_V_FRONTPORCH(x)	(((x) & 0xfff) << 0)
> +#define MALIDP_DE_V_BACKPORCH(x)	(((x) & 0xff) << 16)
> +#define MALIDP_DE_H_SYNCWIDTH(x)	(((x) & 0x3ff) << 0)
> +#define MALIDP_DE_V_SYNCWIDTH(x)	(((x) & 0xff) << 16)
> +#define MALIDP_DE_H_ACTIVE(x)		(((x) & 0x1fff) << 0)
> +#define MALIDP_DE_V_ACTIVE(x)		(((x) & 0x1fff) << 16)
> +
> +/* register offsets and bits specific to DP500 */
> +#define MALIDP500_DC_BASE		0x00000
> +#define MALIDP500_DC_CONTROL		0x0000c
> +#define   MALIDP500_DC_CONFIG_REQ	(1 << 17)
> +#define   MALIDP500_HSYNCPOL		(1 << 20)
> +#define   MALIDP500_VSYNCPOL		(1 << 21)
> +#define   MALIDP500_DC_CLEAR_MASK	0x300fff
> +#define MALIDP500_DE_LINE_COUNTER	0x00010
> +#define MALIDP500_DE_AXI_CONTROL	0x00014
> +#define MALIDP500_DE_SECURE_CTRL	0x0001c
> +#define MALIDP500_DE_CHROMA_KEY		0x00024
> +#define MALIDP500_TIMINGS_BASE		0x00028
> +
> +#define MALIDP500_CONFIG_3D		0x00038
> +#define MALIDP500_BGND_COLOR		0x0003c
> +#define MALIDP500_OUTPUT_DEPTH		0x00044
> +#define MALIDP500_YUV_RGB_COEF		0x00048
> +#define MALIDP500_COLOR_ADJ_COEF	0x00078
> +#define MALIDP500_COEF_TABLE_ADDR	0x000a8
> +#define MALIDP500_COEF_TABLE_DATA	0x000ac
> +#define MALIDP500_DE_LV_BASE		0x00100
> +#define MALIDP500_DE_LV_PTR_BASE	0x00124
> +#define MALIDP500_DE_LG1_BASE		0x00200
> +#define MALIDP500_DE_LG1_PTR_BASE	0x0021c
> +#define MALIDP500_DE_LG2_BASE		0x00300
> +#define MALIDP500_DE_LG2_PTR_BASE	0x0031c
> +#define MALIDP500_SE_BASE		0x00c00
> +#define MALIDP500_SE_PTR_BASE		0x00e0c
> +#define MALIDP500_DC_IRQ_BASE		0x00f00
> +#define MALIDP500_CONFIG_VALID		0x00f00
> +#define MALIDP500_CONFIG_ID		0x00fd4
> +
> +/* register offsets and bits specific to DP550/DP650 */
> +#define MALIDP550_DE_CONTROL		0x00010
> +#define MALIDP550_DE_LINE_COUNTER	0x00014
> +#define MALIDP550_DE_AXI_CONTROL	0x00018
> +#define MALIDP550_DE_QOS		0x0001c
> +#define MALIDP550_TIMINGS_BASE		0x00030
> +#define MALIDP550_HSYNCPOL		(1 << 12)
> +#define MALIDP550_VSYNCPOL		(1 << 28)
> +
> +#define MALIDP550_DE_DISP_SIDEBAND	0x00040
> +#define MALIDP550_DE_BGND_COLOR		0x00044
> +#define MALIDP550_DE_OUTPUT_DEPTH	0x0004c
> +#define MALIDP550_DE_COLOR_COEF		0x00050
> +#define MALIDP550_DE_COEF_TABLE_ADDR	0x00080
> +#define MALIDP550_DE_COEF_TABLE_DATA	0x00084
> +#define MALIDP550_DE_LV1_BASE		0x00100
> +#define MALIDP550_DE_LV1_PTR_BASE	0x00124
> +#define MALIDP550_DE_LV2_BASE		0x00200
> +#define MALIDP550_DE_LV2_PTR_BASE	0x00224
> +#define MALIDP550_DE_LG_BASE		0x00300
> +#define MALIDP550_DE_LG_PTR_BASE	0x0031c
> +#define MALIDP550_DE_LS_BASE		0x00400
> +#define MALIDP550_DE_LS_PTR_BASE	0x0042c
> +#define MALIDP550_DE_PERF_BASE		0x00500
> +#define MALIDP550_SE_BASE		0x08000
> +#define MALIDP550_DC_BASE		0x0c000
> +#define MALIDP550_DC_CONTROL		0x0c010
> +#define   MALIDP550_DC_CONFIG_REQ	(1 << 16)
> +#define MALIDP550_CONFIG_VALID		0x0c014
> +#define MALIDP550_CONFIG_ID		0x0ffd4
> +
> +/*
> + * Starting with DP550 the register map blocks has been standardised to the
> + * following layout:
> + *
> + *   Offset            Block registers
> + *  0x00000            Display Engine
> + *  0x08000            Scaling Engine
> + *  0x0c000            Display Core
> + *  0x10000            Secure control
> + *
> + * The old DP500 IP mixes some DC with the DE registers, hence the need
> + * for a mapping structure.
> + */
> +
> +#endif /* __MALIDP_REGS_H__ */
> -- 
> 2.8.0
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
====================
| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---------------
    ¯\_(ツ)_/¯

From mboxrd@z Thu Jan  1 00:00:00 1970
From: Liviu Dudau <Liviu.Dudau@arm.com>
Subject: Re: [PATCH v2 2/3] drm/arm: Add support for Mali Display Processors
Date: Thu, 19 May 2016 16:26:49 +0100
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T24gTW9uLCBBcHIgMjUsIDIwMTYgYXQgMDM6MTk6MjNQTSArMDEwMCwgTGl2aXUgRHVkYXUgd3Jv
dGU6Cj4gQWRkIHN1cHBvcnQgZm9yIHRoZSBuZXcgZmFtaWx5IG9mIERpc3BsYXkgUHJvY2Vzc29y
cyBmcm9tIEFSTSBMdGQuCj4gVGhpcyBjb21taXQgYWRkcyBiYXNpYyBzdXBwb3J0IGZvciBNYWxp
IERQNTAwLCBEUDU1MCBhbmQgRFA2NTAKPiBwYXJ0cywgd2l0aCBvbmx5IHRoZSBkaXNwbGF5IGVu
Z2luZSBiZWluZyBzdXBwb3J0ZWQgYXQgdGhlIG1vbWVudC4KPiAKPiBDYzogRGF2aWQgQnJvd24g
PERhdmlkLkJyb3duQGFybS5jb20+Cj4gQ2M6IEJyaWFuIFN0YXJrZXkgPEJyaWFuLlN0YXJrZXlA
YXJtLmNvbT4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBMaXZpdSBEdWRhdSA8TGl2aXUuRHVkYXVAYXJt
LmNvbT4KCkhlbGxvLAoKSSdtIGZ1bGx5IGF3YXJlIHRoYXQgdGhlIG1lcmdlIHdpbmRvdyBpcyBv
cGVuIGFuZCBwZW9wbGUgYXJlIGJ1c3ksIGhvd2V2ZXIgaWYKYW55IG9mIHRoZSBEUk0gc3ViLW1h
aW50YWluZXJzIGNvdWxkIHByb3ZpZGUgc29tZSBBY2tzIG9yIFJldmlld2VkLWJ5cyBJIHdvdWxk
CnJlYWxseSBhcHByZWNpYXRlIGl0LgoKSSBwbGFuIHRvIG1ha2UgdGhlIGNvZGUgYXZhaWxhYmxl
IHVuZGVyIGEgbmV3IGJyYW5jaCB0byBnbyBpbnRvIGxpbnV4LW5leHQgbmV4dAp3ZWVrLgoKQmVz
dCByZWdhcmRzLApMaXZpdQoKPiAtLS0KPiAgZHJpdmVycy9ncHUvZHJtL2FybS9LY29uZmlnICAg
ICAgICAgfCAgMTYgKwo+ICBkcml2ZXJzL2dwdS9kcm0vYXJtL01ha2VmaWxlICAgICAgICB8ICAg
MiArCj4gIGRyaXZlcnMvZ3B1L2RybS9hcm0vbWFsaWRwX2NydGMuYyAgIHwgMjU5ICsrKysrKysr
KysrKwo+ICBkcml2ZXJzL2dwdS9kcm0vYXJtL21hbGlkcF9kcnYuYyAgICB8IDUzOCArKysrKysr
KysrKysrKysrKysrKysrKysrCj4gIGRyaXZlcnMvZ3B1L2RybS9hcm0vbWFsaWRwX2Rydi5oICAg
IHwgIDU0ICsrKwo+ICBkcml2ZXJzL2dwdS9kcm0vYXJtL21hbGlkcF9ody5jICAgICB8IDc3NCAr
KysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysKPiAgZHJpdmVycy9ncHUvZHJtL2Fy
bS9tYWxpZHBfaHcuaCAgICAgfCAxODkgKysrKysrKysrCj4gIGRyaXZlcnMvZ3B1L2RybS9hcm0v
bWFsaWRwX3BsYW5lcy5jIHwgMzM3ICsrKysrKysrKysrKysrKysKPiAgZHJpdmVycy9ncHUvZHJt
L2FybS9tYWxpZHBfcmVncy5oICAgfCAxNzIgKysrKysrKysKPiAgOSBmaWxlcyBjaGFuZ2VkLCAy
MzQxIGluc2VydGlvbnMoKykKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZ3B1L2RybS9h
cm0vbWFsaWRwX2NydGMuYwo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL2Fy
bS9tYWxpZHBfZHJ2LmMKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvZ3B1L2RybS9hcm0v
bWFsaWRwX2Rydi5oCj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2dwdS9kcm0vYXJtL21h
bGlkcF9ody5jCj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2dwdS9kcm0vYXJtL21hbGlk
cF9ody5oCj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2dwdS9kcm0vYXJtL21hbGlkcF9w
bGFuZXMuYwo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJtL2FybS9tYWxpZHBf
cmVncy5oCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9hcm0vS2NvbmZpZyBiL2Ry
aXZlcnMvZ3B1L2RybS9hcm0vS2NvbmZpZwo+IGluZGV4IGVhZWQ0NTQuLjFiMjkwNjUgMTAwNjQ0
Cj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2FybS9LY29uZmlnCj4gKysrIGIvZHJpdmVycy9ncHUv
ZHJtL2FybS9LY29uZmlnCj4gQEAgLTI1LDMgKzI1LDE5IEBAIGNvbmZpZyBEUk1fSERMQ0RfU0hP
V19VTkRFUlJVTgo+ICAJICBFbmFibGUgdGhpcyBvcHRpb24gdG8gc2hvdyBpbiByZWQgY29sb3Vy
IHRoZSBwaXhlbHMgdGhhdCB0aGUKPiAgCSAgSERMQ0QgZGV2aWNlIGRpZCBub3QgZmV0Y2ggZnJv
bSBmcmFtZWJ1ZmZlciBkdWUgdG8gdW5kZXJydW4KPiAgCSAgY29uZGl0aW9ucy4KPiArCj4gK2Nv
bmZpZyBEUk1fTUFMSV9ESVNQTEFZCj4gKwl0cmlzdGF0ZSAiQVJNIE1hbGkgRGlzcGxheSBQcm9j
ZXNzb3IiCj4gKwlkZXBlbmRzIG9uIERSTSAmJiBPRiAmJiAoQVJNIHx8IEFSTTY0KQo+ICsJZGVw
ZW5kcyBvbiBDT01NT05fQ0xLCj4gKwlzZWxlY3QgRFJNX0FSTQo+ICsJc2VsZWN0IERSTV9LTVNf
SEVMUEVSCj4gKwlzZWxlY3QgRFJNX0tNU19DTUFfSEVMUEVSCj4gKwlzZWxlY3QgRFJNX0dFTV9D
TUFfSEVMUEVSCj4gKwlzZWxlY3QgVklERU9NT0RFX0hFTFBFUlMKPiArCWhlbHAKPiArCSAgQ2hv
b3NlIHRoaXMgb3B0aW9uIGlmIHlvdSB3YW50IHRvIGNvbXBpbGUgdGhlIEFSTSBNYWxpIERpc3Bs
YXkKPiArCSAgUHJvY2Vzc29yIGRyaXZlci4gSXQgc3VwcG9ydHMgdGhlIERQNTAwLCBEUDU1MCBh
bmQgRFA2NTAgdmFyaWFudHMKPiArCSAgb2YgdGhlIGhhcmR3YXJlLgo+ICsKPiArCSAgSWYgY29t
cGlsZWQgYXMgYSBtb2R1bGUgaXQgd2lsbCBiZSBjYWxsZWQgbWFsaS1kcC4KPiBkaWZmIC0tZ2l0
IGEvZHJpdmVycy9ncHUvZHJtL2FybS9NYWtlZmlsZSBiL2RyaXZlcnMvZ3B1L2RybS9hcm0vTWFr
ZWZpbGUKPiBpbmRleCA4OWRjYjdiLi5iYjhiMTU4IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1
L2RybS9hcm0vTWFrZWZpbGUKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vYXJtL01ha2VmaWxlCj4g
QEAgLTEsMiArMSw0IEBACj4gIGhkbGNkLXkgOj0gaGRsY2RfZHJ2Lm8gaGRsY2RfY3J0Yy5vCj4g
IG9iai0kKENPTkZJR19EUk1fSERMQ0QpCSs9IGhkbGNkLm8KPiArbWFsaS1kcC15IDo9IG1hbGlk
cF9kcnYubyBtYWxpZHBfaHcubyBtYWxpZHBfcGxhbmVzLm8gbWFsaWRwX2NydGMubwo+ICtvYmot
JChDT05GSUdfRFJNX01BTElfRElTUExBWSkJKz0gbWFsaS1kcC5vCj4gZGlmZiAtLWdpdCBhL2Ry
aXZlcnMvZ3B1L2RybS9hcm0vbWFsaWRwX2NydGMuYyBiL2RyaXZlcnMvZ3B1L2RybS9hcm0vbWFs
aWRwX2NydGMuYwo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gaW5kZXggMDAwMDAwMC4uMTI4OTNk
MAo+IC0tLSAvZGV2L251bGwKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vYXJtL21hbGlkcF9jcnRj
LmMKPiBAQCAtMCwwICsxLDI1OSBAQAo+ICsvKgo+ICsgKiAoQykgQ09QWVJJR0hUIDIwMTYgQVJN
IExpbWl0ZWQuIEFsbCByaWdodHMgcmVzZXJ2ZWQuCj4gKyAqIEF1dGhvcjogTGl2aXUgRHVkYXUg
PExpdml1LkR1ZGF1QGFybS5jb20+Cj4gKyAqCj4gKyAqIFRoaXMgcHJvZ3JhbSBpcyBmcmVlIHNv
ZnR3YXJlIGFuZCBpcyBwcm92aWRlZCB0byB5b3UgdW5kZXIgdGhlIHRlcm1zIG9mIHRoZQo+ICsg
KiBHTlUgR2VuZXJhbCBQdWJsaWMgTGljZW5zZSB2ZXJzaW9uIDIgYXMgcHVibGlzaGVkIGJ5IHRo
ZSBGcmVlIFNvZnR3YXJlCj4gKyAqIEZvdW5kYXRpb24sIGFuZCBhbnkgdXNlIGJ5IHlvdSBvZiB0
aGlzIHByb2dyYW0gaXMgc3ViamVjdCB0byB0aGUgdGVybXMKPiArICogb2Ygc3VjaCBHTlUgbGlj
ZW5jZS4KPiArICoKPiArICogQVJNIE1hbGkgRFA1MDAvRFA1NTAvRFA2NTAgZHJpdmVyIChjcnRj
IG9wZXJhdGlvbnMpCj4gKyAqLwo+ICsKPiArI2luY2x1ZGUgPGRybS9kcm1QLmg+Cj4gKyNpbmNs
dWRlIDxkcm0vZHJtX2F0b21pYy5oPgo+ICsjaW5jbHVkZSA8ZHJtL2RybV9hdG9taWNfaGVscGVy
Lmg+Cj4gKyNpbmNsdWRlIDxkcm0vZHJtX2NydGMuaD4KPiArI2luY2x1ZGUgPGRybS9kcm1fY3J0
Y19oZWxwZXIuaD4KPiArI2luY2x1ZGUgPGxpbnV4L2Nsay5oPgo+ICsjaW5jbHVkZSA8dmlkZW8v
dmlkZW9tb2RlLmg+Cj4gKwo+ICsjaW5jbHVkZSAibWFsaWRwX2Rydi5oIgo+ICsjaW5jbHVkZSAi
bWFsaWRwX2h3LmgiCj4gKwo+ICtzdGF0aWMgYm9vbCBtYWxpZHBfY3J0Y19tb2RlX2ZpeHVwKHN0
cnVjdCBkcm1fY3J0YyAqY3J0YywKPiArCQkJCSAgIGNvbnN0IHN0cnVjdCBkcm1fZGlzcGxheV9t
b2RlICptb2RlLAo+ICsJCQkJICAgc3RydWN0IGRybV9kaXNwbGF5X21vZGUgKmFkanVzdGVkX21v
ZGUpCj4gK3sKPiArCXN0cnVjdCBtYWxpZHBfZHJtICptYWxpZHAgPSBjcnRjX3RvX21hbGlkcF9k
ZXZpY2UoY3J0Yyk7Cj4gKwlzdHJ1Y3QgbWFsaWRwX2h3X2RldmljZSAqaHdkZXYgPSBtYWxpZHAt
PmRldjsKPiArCj4gKwkvKgo+ICsJICogY2hlY2sgdGhhdCB0aGUgaGFyZHdhcmUgY2FuIGRyaXZl
IHRoZSByZXF1aXJlZCBjbG9jayByYXRlLAo+ICsJICogYnV0IHNraXAgdGhlIGNoZWNrIGlmIHRo
ZSBjbG9jayBpcyBtZWFudCB0byBiZSBkaXNhYmxlZCAocmVxX3JhdGUgPSAwKQo+ICsJICovCj4g
Kwlsb25nIHJhdGUsIHJlcV9yYXRlID0gbW9kZS0+Y3J0Y19jbG9jayAqIDEwMDA7Cj4gKwo+ICsJ
aWYgKHJlcV9yYXRlKSB7Cj4gKwkJcmF0ZSA9IGNsa19yb3VuZF9yYXRlKGh3ZGV2LT5tY2xrLCBy
ZXFfcmF0ZSk7Cj4gKwkJaWYgKHJhdGUgPCByZXFfcmF0ZSkgewo+ICsJCQlEUk1fREVCVUdfRFJJ
VkVSKCJtY2xrIGNsb2NrIHVuYWJsZSB0byByZWFjaCAlZCBrSHpcbiIsCj4gKwkJCQkJIG1vZGUt
PmNydGNfY2xvY2spOwo+ICsJCQlyZXR1cm4gZmFsc2U7Cj4gKwkJfQo+ICsKPiArCQlyYXRlID0g
Y2xrX3JvdW5kX3JhdGUoaHdkZXYtPnB4bGNsaywgcmVxX3JhdGUpOwo+ICsJCWlmIChyYXRlICE9
IHJlcV9yYXRlKSB7Cj4gKwkJCURSTV9ERUJVR19EUklWRVIoInB4bGNsayBkb2Vzbid0IHN1cHBv
cnQgJWxkIEh6XG4iLAo+ICsJCQkJCSByZXFfcmF0ZSk7Cj4gKwkJCXJldHVybiBmYWxzZTsKPiAr
CQl9Cj4gKwl9Cj4gKwo+ICsJcmV0dXJuIHRydWU7Cj4gK30KPiArCj4gK3N0YXRpYyB2b2lkIG1h
bGlkcF9jcnRjX2VuYWJsZShzdHJ1Y3QgZHJtX2NydGMgKmNydGMpCj4gK3sKPiArCXN0cnVjdCBt
YWxpZHBfZHJtICptYWxpZHAgPSBjcnRjX3RvX21hbGlkcF9kZXZpY2UoY3J0Yyk7Cj4gKwlzdHJ1
Y3QgbWFsaWRwX2h3X2RldmljZSAqaHdkZXYgPSBtYWxpZHAtPmRldjsKPiArCXN0cnVjdCB2aWRl
b21vZGUgdm07Cj4gKwo+ICsJZHJtX2Rpc3BsYXlfbW9kZV90b192aWRlb21vZGUoJmNydGMtPnN0
YXRlLT5hZGp1c3RlZF9tb2RlLCAmdm0pOwo+ICsKPiArCWNsa19wcmVwYXJlX2VuYWJsZShod2Rl
di0+cHhsY2xrKTsKPiArCj4gKwkvKiBtY2xrIG5lZWRzIHRvIGJlIHNldCB0byB0aGUgc2FtZSBv
ciBoaWdoZXIgcmF0ZSB0aGFuIHB4bGNsayAqLwo+ICsJY2xrX3NldF9yYXRlKGh3ZGV2LT5tY2xr
LCBjcnRjLT5zdGF0ZS0+YWRqdXN0ZWRfbW9kZS5jcnRjX2Nsb2NrICogMTAwMCk7Cj4gKwljbGtf
c2V0X3JhdGUoaHdkZXYtPnB4bGNsaywgY3J0Yy0+c3RhdGUtPmFkanVzdGVkX21vZGUuY3J0Y19j
bG9jayAqIDEwMDApOwo+ICsKPiArCWh3ZGV2LT5tb2Rlc2V0KGh3ZGV2LCAmdm0pOwo+ICsJaHdk
ZXYtPmxlYXZlX2NvbmZpZ19tb2RlKGh3ZGV2KTsKPiArfQo+ICsKPiArc3RhdGljIHZvaWQgbWFs
aWRwX2NydGNfZGlzYWJsZShzdHJ1Y3QgZHJtX2NydGMgKmNydGMpCj4gK3sKPiArCXN0cnVjdCBt
YWxpZHBfZHJtICptYWxpZHAgPSBjcnRjX3RvX21hbGlkcF9kZXZpY2UoY3J0Yyk7Cj4gKwlzdHJ1
Y3QgbWFsaWRwX2h3X2RldmljZSAqaHdkZXYgPSBtYWxpZHAtPmRldjsKPiArCj4gKwkvKgo+ICsJ
ICogYXZvaWQgZGlzYWJsaW5nIGFscmVhZHkgZGlzYWJsZWQgY2xvY2tzIGFuZCBoYXJkd2FyZQo+
ICsJICogKGFzIGlzIHRoZSBjYXNlIGF0IGRldmljZSBwcm9iZSB0aW1lKQo+ICsJICovCj4gKwlp
ZiAoY3J0Yy0+c3RhdGUtPmFjdGl2ZSkgewo+ICsJCWh3ZGV2LT5lbnRlcl9jb25maWdfbW9kZSho
d2Rldik7Cj4gKwkJY2xrX2Rpc2FibGVfdW5wcmVwYXJlKGh3ZGV2LT5weGxjbGspOwo+ICsJfQo+
ICt9Cj4gKwo+ICtzdGF0aWMgaW50IG1hbGlkcF9jcnRjX2F0b21pY19jaGVjayhzdHJ1Y3QgZHJt
X2NydGMgKmNydGMsCj4gKwkJCQkgICAgc3RydWN0IGRybV9jcnRjX3N0YXRlICpzdGF0ZSkKPiAr
ewo+ICsJc3RydWN0IG1hbGlkcF9kcm0gKm1hbGlkcCA9IGNydGNfdG9fbWFsaWRwX2RldmljZShj
cnRjKTsKPiArCXN0cnVjdCBtYWxpZHBfaHdfZGV2aWNlICpod2RldiA9IG1hbGlkcC0+ZGV2Owo+
ICsJc3RydWN0IGRybV9wbGFuZSAqcGxhbmU7Cj4gKwlzdHJ1Y3QgZHJtX3BsYW5lX3N0YXRlICpw
c3RhdGU7Cj4gKwl1MzIgcm90X21lbV9mcmVlLCByb3RfbWVtX3VzYWJsZTsKPiArCWludCByb3Rh
dGVkX3BsYW5lcyA9IDA7Cj4gKwo+ICsJLyoKPiArCSAqIGNoZWNrIGlmIHRoZXJlIGlzIGVub3Vn
aCByb3RhdGlvbiBtZW1vcnkgYXZhaWxhYmxlIGZvciBwbGFuZXMKPiArCSAqIHRoYXQgbmVlZCA5
MMKwIGFuZCAyNzDCsCByb3RhdGlvbi4gRWFjaCBwbGFuZSBoYXMgc2V0IGl0cyByZXF1aXJlZAo+
ICsJICogbWVtb3J5IHNpemUgaW4gdGhlIC0+cGxhbmVfY2hlY2soKSBjYWxsYmFjaywgaGVyZSB3
ZSBvbmx5IG1ha2UKPiArCSAqIHN1cmUgdGhhdCB0aGUgc3VtcyBhcmUgbGVzcyB0aGF0IHRoZSB0
b3RhbCB1c2FibGUgbWVtb3J5Lgo+ICsJICoKPiArCSAqIFRoZSByb3RhdGlvbiBtZW1vcnkgYWxs
b2NhdGlvbiBhbGdvcml0aG0gKGZvciBlYWNoIHBsYW5lKToKPiArCSAqICBhLiBJZiBubyBtb3Jl
IHJvdGF0ZWQgcGxhbmVzIGV4aXN0LCBhbGwgcmVtYWluaW5nIHJvdGF0ZQo+ICsJICogICAgIG1l
bW9yeSBpbiB0aGUgYmFuayBpcyBhdmFpbGFibGUgZm9yIHVzZSBieSB0aGUgcGxhbmUuCj4gKwkg
KiAgYi4gSWYgb3RoZXIgcm90YXRlZCBwbGFuZXMgZXhpc3QsIGFuZCBwbGFuZSdzIGxheWVyIElE
IGlzCj4gKwkgKiAgICAgREVfVklERU8xLCBpdCBjYW4gdXNlIGFsbCB0aGUgbWVtb3J5IGZyb20g
Zmlyc3QgYmFuayBpZgo+ICsJICogICAgIHNlY29uZGFyeSByb3RhdGlvbiBtZW1vcnkgYmFuayBp
cyBhdmFpbGFibGUsIG90aGVyd2lzZSBpdCBjYW4KPiArCSAqICAgICB1c2UgdXAgdG8gaGFsZiB0
aGUgYmFuaydzIG1lbW9yeS4KPiArCSAqICBjLiBJZiBvdGhlciByb3RhdGVkIHBsYW5lcyBleGlz
dCwgYW5kIHBsYW5lJ3MgbGF5ZXIgSUQgaXMgbm90Cj4gKwkgKiAgICAgREVfVklERU8xLCBpdCBj
YW4gdXNlIGhhbGYgb2YgdGhlIGF2YWlsYWJsZSBtZW1vcnkKPiArCSAqCj4gKwkgKiBOb3RlOiB0
aGlzIGFsZ29yaXRobSBhc3N1bWVzIHRoYXQgdGhlIG9yZGVyIGluIHdoaWNoIHRoZSBwbGFuZXMg
YXJlCj4gKwkgKiBjaGVja2VkIGFsd2F5cyBoYXMgREVfVklERU8xIHBsYW5lIGZpcnN0IGluIHRo
ZSBsaXN0IGlmIGl0IGlzCj4gKwkgKiByb3RhdGVkLiBCZWNhdXNlIHRoYXQgaXMgaG93IHdlIGNy
ZWF0ZSB0aGUgcGxhbmVzIGluIHRoZSBmaXJzdAo+ICsJICogcGxhY2UsIHVuZGVyIGN1cnJlbnQg
RFJNIHZlcnNpb24gdGhpbmdzIHdvcmssIGJ1dCBpZiBldmVyIHRoZSBvcmRlcgo+ICsJICogaW4g
d2hpY2ggZHJtX2F0b21pY19jcnRjX3N0YXRlX2Zvcl9lYWNoX3BsYW5lKCkgaXRlcmF0ZXMgb3Zl
ciBwbGFuZXMKPiArCSAqIGNoYW5nZXMsIHdlIG5lZWQgdG8gcHJlLXNvcnQgdGhlIHBsYW5lcyBi
ZWZvcmUgdmFsaWRhdGlvbi4KPiArCSAqLwo+ICsKPiArCS8qIGZpcnN0IGNvdW50IHRoZSBudW1i
ZXIgb2Ygcm90YXRlZCBwbGFuZXMgKi8KPiArCWRybV9hdG9taWNfY3J0Y19zdGF0ZV9mb3JfZWFj
aF9wbGFuZShwbGFuZSwgc3RhdGUpIHsKPiArCQlwc3RhdGUgPSBkcm1fYXRvbWljX2dldF9wbGFu
ZV9zdGF0ZShzdGF0ZS0+c3RhdGUsIHBsYW5lKTsKPiArCQlpZiAocHN0YXRlLT5yb3RhdGlvbiAm
IE1BTElEUF9ST1RBVEVEX01BU0spCj4gKwkJCXJvdGF0ZWRfcGxhbmVzKys7Cj4gKwl9Cj4gKwo+
ICsJcm90X21lbV9mcmVlID0gaHdkZXYtPnJvdGF0aW9uX21lbW9yeVswXTsKPiArCS8qCj4gKwkg
KiBpZiB3ZSBoYXZlIG1vcmUgdGhhbiAxIHBsYW5lIHVzaW5nIHJvdGF0aW9uIG1lbW9yeSwgdXNl
IHRoZSBzZWNvbmQKPiArCSAqIGJsb2NrIG9mIHJvdGF0aW9uIG1lbW9yeSBhcyB3ZWxsCj4gKwkg
Ki8KPiArCWlmIChyb3RhdGVkX3BsYW5lcyA+IDEpCj4gKwkJcm90X21lbV9mcmVlICs9IGh3ZGV2
LT5yb3RhdGlvbl9tZW1vcnlbMV07Cj4gKwo+ICsJLyogbm93IHZhbGlkYXRlIHRoZSByb3RhdGlv
biBtZW1vcnkgcmVxdWlyZW1lbnRzICovCj4gKwlkcm1fYXRvbWljX2NydGNfc3RhdGVfZm9yX2Vh
Y2hfcGxhbmUocGxhbmUsIHN0YXRlKSB7Cj4gKwkJc3RydWN0IG1hbGlkcF9wbGFuZSAqbXAgPSB0
b19tYWxpZHBfcGxhbmUocGxhbmUpOwo+ICsKPiArCQlwc3RhdGUgPSBkcm1fYXRvbWljX2dldF9w
bGFuZV9zdGF0ZShzdGF0ZS0+c3RhdGUsIHBsYW5lKTsKPiArCQlpZiAocHN0YXRlLT5yb3RhdGlv
biAmIE1BTElEUF9ST1RBVEVEX01BU0spIHsKPiArCQkJLyogcHJvY2VzcyBjdXJyZW50IHBsYW5l
ICovCj4gKwkJCXJvdGF0ZWRfcGxhbmVzLS07Cj4gKwo+ICsJCQlpZiAoIXJvdGF0ZWRfcGxhbmVz
KSB7Cj4gKwkJCQkvKiBubyBtb3JlIHJvdGF0ZWQgcGxhbmVzLCB3ZSBjYW4gdXNlIHdoYXQncyBs
ZWZ0ICovCj4gKwkJCQlyb3RfbWVtX3VzYWJsZSA9IHJvdF9tZW1fZnJlZTsKPiArCQkJfSBlbHNl
IHsKPiArCQkJCWlmICgobXAtPmxheWVyLT5pZCAhPSBERV9WSURFTzEpIHx8Cj4gKwkJCQkgICAg
KGh3ZGV2LT5yb3RhdGlvbl9tZW1vcnlbMV0gPT0gMCkpCj4gKwkJCQkJcm90X21lbV91c2FibGUg
PSByb3RfbWVtX2ZyZWUgLyAyOwo+ICsJCQkJZWxzZQo+ICsJCQkJCXJvdF9tZW1fdXNhYmxlID0g
aHdkZXYtPnJvdGF0aW9uX21lbW9yeVswXTsKPiArCQkJfQo+ICsKPiArCQkJcm90X21lbV9mcmVl
IC09IHJvdF9tZW1fdXNhYmxlOwo+ICsKPiArCQkJaWYgKG1wLT5yb3RtZW1fc2l6ZSA+IHJvdF9t
ZW1fdXNhYmxlKQo+ICsJCQkJcmV0dXJuIC1FSU5WQUw7Cj4gKwkJfQo+ICsJfQo+ICsKPiArCXJl
dHVybiAwOwo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCBtYWxpZHBfY3J0Y19hdG9taWNfYmVnaW4o
c3RydWN0IGRybV9jcnRjICpjcnRjLAo+ICsJCQkJICAgICBzdHJ1Y3QgZHJtX2NydGNfc3RhdGUg
Km9sZF9zdGF0ZSkKPiArewo+ICsJc3RydWN0IG1hbGlkcF9kcm0gKm1hbGlkcCA9IGNydGNfdG9f
bWFsaWRwX2RldmljZShjcnRjKTsKPiArCj4gKwlpZiAoY3J0Yy0+c3RhdGUtPmV2ZW50KSB7Cj4g
KwkJc3RydWN0IGRybV9wZW5kaW5nX3ZibGFua19ldmVudCAqZXZlbnQgPSBjcnRjLT5zdGF0ZS0+
ZXZlbnQ7Cj4gKwkJdW5zaWduZWQgbG9uZyBmbGFnczsKPiArCj4gKwkJY3J0Yy0+c3RhdGUtPmV2
ZW50ID0gTlVMTDsKPiArCQlldmVudC0+cGlwZSA9IGRybV9jcnRjX2luZGV4KGNydGMpOwo+ICsK
PiArCQlXQVJOX09OKGRybV9jcnRjX3ZibGFua19nZXQoY3J0YykgIT0gMCk7Cj4gKwo+ICsJCXNw
aW5fbG9ja19pcnFzYXZlKCZjcnRjLT5kZXYtPmV2ZW50X2xvY2ssIGZsYWdzKTsKPiArCQlsaXN0
X2FkZF90YWlsKCZldmVudC0+YmFzZS5saW5rLCAmbWFsaWRwLT5ldmVudF9saXN0KTsKPiArCQlz
cGluX3VubG9ja19pcnFyZXN0b3JlKCZjcnRjLT5kZXYtPmV2ZW50X2xvY2ssIGZsYWdzKTsKPiAr
CX0KPiArfQo+ICsKPiArc3RhdGljIHZvaWQgbWFsaWRwX2NydGNfYXRvbWljX2ZsdXNoKHN0cnVj
dCBkcm1fY3J0YyAqY3J0YywKPiArCQkJCSAgICAgc3RydWN0IGRybV9jcnRjX3N0YXRlICpvbGRf
c3RhdGUpCj4gK3sKPiArCXN0cnVjdCBtYWxpZHBfZHJtICptYWxpZHAgPSBjcnRjX3RvX21hbGlk
cF9kZXZpY2UoY3J0Yyk7Cj4gKwlzdHJ1Y3QgZHJtX2RldmljZSAqZHJtID0gY3J0Yy0+ZGV2Owo+
ICsJaW50IHJldCA9IG1hbGlkcF9zZXRfYW5kX3dhaXRfY29uZmlnX3ZhbGlkKGRybSk7Cj4gKwo+
ICsJaWYgKCFyZXQpIHsKPiArCQl1bnNpZ25lZCBsb25nIGZsYWdzOwo+ICsJCXN0cnVjdCBkcm1f
cGVuZGluZ192YmxhbmtfZXZlbnQgKmU7Cj4gKwo+ICsJCXNwaW5fbG9ja19pcnFzYXZlKCZkcm0t
PmV2ZW50X2xvY2ssIGZsYWdzKTsKPiArCQllID0gbGlzdF9maXJzdF9lbnRyeV9vcl9udWxsKCZt
YWxpZHAtPmV2ZW50X2xpc3QsIHR5cGVvZigqZSksCj4gKwkJCQkJICAgICBiYXNlLmxpbmspOwo+
ICsJCWlmIChlKSB7Cj4gKwkJCWxpc3RfZGVsKCZlLT5iYXNlLmxpbmspOwo+ICsJCQlkcm1fY3J0
Y19zZW5kX3ZibGFua19ldmVudCgmbWFsaWRwLT5jcnRjLCBlKTsKPiArCQkJZHJtX2NydGNfdmJs
YW5rX3B1dCgmbWFsaWRwLT5jcnRjKTsKPiArCQl9Cj4gKwkJc3Bpbl91bmxvY2tfaXJxcmVzdG9y
ZSgmZHJtLT5ldmVudF9sb2NrLCBmbGFncyk7Cj4gKwl9IGVsc2Ugewo+ICsJCURSTV9ERUJVR19E
UklWRVIoInRpbWVkIG91dCB3YWl0aW5nIGZvciB1cGRhdGVkIGNvbmZpZ3VyYXRpb25cbiIpOwo+
ICsJfQo+ICt9Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IGRybV9jcnRjX2hlbHBlcl9mdW5j
cyBtYWxpZHBfY3J0Y19oZWxwZXJfZnVuY3MgPSB7Cj4gKwkubW9kZV9maXh1cCA9IG1hbGlkcF9j
cnRjX21vZGVfZml4dXAsCj4gKwkuZW5hYmxlID0gbWFsaWRwX2NydGNfZW5hYmxlLAo+ICsJLmRp
c2FibGUgPSBtYWxpZHBfY3J0Y19kaXNhYmxlLAo+ICsJLmF0b21pY19jaGVjayA9IG1hbGlkcF9j
cnRjX2F0b21pY19jaGVjaywKPiArCS5hdG9taWNfYmVnaW4gPSBtYWxpZHBfY3J0Y19hdG9taWNf
YmVnaW4sCj4gKwkuYXRvbWljX2ZsdXNoID0gbWFsaWRwX2NydGNfYXRvbWljX2ZsdXNoLAo+ICt9
Owo+ICsKPiArc3RhdGljIGNvbnN0IHN0cnVjdCBkcm1fY3J0Y19mdW5jcyBtYWxpZHBfY3J0Y19m
dW5jcyA9IHsKPiArCS5kZXN0cm95ID0gZHJtX2NydGNfY2xlYW51cCwKPiArCS5zZXRfY29uZmln
ID0gZHJtX2F0b21pY19oZWxwZXJfc2V0X2NvbmZpZywKPiArCS5wYWdlX2ZsaXAgPSBkcm1fYXRv
bWljX2hlbHBlcl9wYWdlX2ZsaXAsCj4gKwkucmVzZXQgPSBkcm1fYXRvbWljX2hlbHBlcl9jcnRj
X3Jlc2V0LAo+ICsJLmF0b21pY19kdXBsaWNhdGVfc3RhdGUgPSBkcm1fYXRvbWljX2hlbHBlcl9j
cnRjX2R1cGxpY2F0ZV9zdGF0ZSwKPiArCS5hdG9taWNfZGVzdHJveV9zdGF0ZSA9IGRybV9hdG9t
aWNfaGVscGVyX2NydGNfZGVzdHJveV9zdGF0ZSwKPiArfTsKPiArCj4gK2ludCBtYWxpZHBfY3J0
Y19pbml0KHN0cnVjdCBkcm1fZGV2aWNlICpkcm0pCj4gK3sKPiArCXN0cnVjdCBtYWxpZHBfZHJt
ICptYWxpZHAgPSBkcm0tPmRldl9wcml2YXRlOwo+ICsJc3RydWN0IGRybV9wbGFuZSAqcHJpbWFy
eSA9IE5VTEwsICpwbGFuZTsKPiArCWludCByZXQ7Cj4gKwo+ICsJZHJtX2Zvcl9lYWNoX3BsYW5l
KHBsYW5lLCBkcm0pIHsKPiArCQlpZiAocGxhbmUtPnR5cGUgPT0gRFJNX1BMQU5FX1RZUEVfUFJJ
TUFSWSkgewo+ICsJCQlwcmltYXJ5ID0gcGxhbmU7Cj4gKwkJCWJyZWFrOwo+ICsJCX0KPiArCX0K
PiArCj4gKwlpZiAoIXByaW1hcnkpIHsKPiArCQlEUk1fRVJST1IoIm5vIHByaW1hcnkgcGxhbmUg
Zm91bmRcbiIpOwo+ICsJCXJldHVybiAtRUlOVkFMOwo+ICsJfQo+ICsKPiArCXJldCA9IGRybV9j
cnRjX2luaXRfd2l0aF9wbGFuZXMoZHJtLCAmbWFsaWRwLT5jcnRjLCBwcmltYXJ5LCBOVUxMLAo+
ICsJCQkJCSZtYWxpZHBfY3J0Y19mdW5jcywgTlVMTCk7Cj4gKwo+ICsJaWYgKHJldCkgewo+ICsJ
CW1hbGlkcF9kZV9wbGFuZXNfZGVzdHJveShkcm0pOwo+ICsJCXJldHVybiByZXQ7Cj4gKwl9Cj4g
Kwo+ICsJZHJtX2NydGNfaGVscGVyX2FkZCgmbWFsaWRwLT5jcnRjLCAmbWFsaWRwX2NydGNfaGVs
cGVyX2Z1bmNzKTsKPiArCXJldHVybiAwOwo+ICt9Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1
L2RybS9hcm0vbWFsaWRwX2Rydi5jIGIvZHJpdmVycy9ncHUvZHJtL2FybS9tYWxpZHBfZHJ2LmMK
PiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+IGluZGV4IDAwMDAwMDAuLjEwZmZiODEKPiAtLS0gL2Rl
di9udWxsCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2FybS9tYWxpZHBfZHJ2LmMKPiBAQCAtMCww
ICsxLDUzOCBAQAo+ICsvKgo+ICsgKiAoQykgQ09QWVJJR0hUIDIwMTYgQVJNIExpbWl0ZWQuIEFs
bCByaWdodHMgcmVzZXJ2ZWQuCj4gKyAqIEF1dGhvcjogTGl2aXUgRHVkYXUgPExpdml1LkR1ZGF1
QGFybS5jb20+Cj4gKyAqCj4gKyAqIFRoaXMgcHJvZ3JhbSBpcyBmcmVlIHNvZnR3YXJlIGFuZCBp
cyBwcm92aWRlZCB0byB5b3UgdW5kZXIgdGhlIHRlcm1zIG9mIHRoZQo+ICsgKiBHTlUgR2VuZXJh
bCBQdWJsaWMgTGljZW5zZSB2ZXJzaW9uIDIgYXMgcHVibGlzaGVkIGJ5IHRoZSBGcmVlIFNvZnR3
YXJlCj4gKyAqIEZvdW5kYXRpb24sIGFuZCBhbnkgdXNlIGJ5IHlvdSBvZiB0aGlzIHByb2dyYW0g
aXMgc3ViamVjdCB0byB0aGUgdGVybXMKPiArICogb2Ygc3VjaCBHTlUgbGljZW5jZS4KPiArICoK
PiArICogQVJNIE1hbGkgRFA1MDAvRFA1NTAvRFA2NTAgS01TL0RSTSBkcml2ZXIKPiArICovCj4g
Kwo+ICsjaW5jbHVkZSA8bGludXgvbW9kdWxlLmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9jbGsuaD4K
PiArI2luY2x1ZGUgPGxpbnV4L2NvbXBvbmVudC5oPgo+ICsjaW5jbHVkZSA8bGludXgvb2ZfZGV2
aWNlLmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9vZl9ncmFwaC5oPgo+ICsjaW5jbHVkZSA8bGludXgv
b2ZfcmVzZXJ2ZWRfbWVtLmg+Cj4gKwo+ICsjaW5jbHVkZSA8ZHJtL2RybVAuaD4KPiArI2luY2x1
ZGUgPGRybS9kcm1fYXRvbWljLmg+Cj4gKyNpbmNsdWRlIDxkcm0vZHJtX2F0b21pY19oZWxwZXIu
aD4KPiArI2luY2x1ZGUgPGRybS9kcm1fY3J0Yy5oPgo+ICsjaW5jbHVkZSA8ZHJtL2RybV9jcnRj
X2hlbHBlci5oPgo+ICsjaW5jbHVkZSA8ZHJtL2RybV9mYl9oZWxwZXIuaD4KPiArI2luY2x1ZGUg
PGRybS9kcm1fZmJfY21hX2hlbHBlci5oPgo+ICsjaW5jbHVkZSA8ZHJtL2RybV9nZW1fY21hX2hl
bHBlci5oPgo+ICsjaW5jbHVkZSA8ZHJtL2RybV9vZi5oPgo+ICsKPiArI2luY2x1ZGUgIm1hbGlk
cF9kcnYuaCIKPiArI2luY2x1ZGUgIm1hbGlkcF9yZWdzLmgiCj4gKyNpbmNsdWRlICJtYWxpZHBf
aHcuaCIKPiArCj4gKyNkZWZpbmUgTUFMSURQX0NPTkZfVkFMSURfVElNRU9VVAkyNTAKPiArCj4g
Ky8qCj4gKyAqIHNldCB0aGUgImNvbmZpZyB2YWxpZCIgYml0IGFuZCB3YWl0IHVudGlsIHRoZSBo
YXJkd2FyZQo+ICsgKiBhY3RzIG9uIGl0Cj4gKyAqLwo+ICtpbnQgbWFsaWRwX3NldF9hbmRfd2Fp
dF9jb25maWdfdmFsaWQoc3RydWN0IGRybV9kZXZpY2UgKmRybSkKPiArewo+ICsJc3RydWN0IG1h
bGlkcF9kcm0gKm1hbGlkcCA9IGRybS0+ZGV2X3ByaXZhdGU7Cj4gKwlzdHJ1Y3QgbWFsaWRwX2h3
X2RldmljZSAqaHdkZXYgPSBtYWxpZHAtPmRldjsKPiArCWludCByZXQ7Cj4gKwo+ICsJaHdkZXYt
PnNldF9jb25maWdfdmFsaWQoaHdkZXYpOwo+ICsJLyogZG9uJ3Qgd2FpdCBmb3IgY29uZmlnX3Zh
bGlkIGZsYWcgaWYgd2UgYXJlIGluIGNvbmZpZyBtb2RlICovCj4gKwlpZiAoaHdkZXYtPmluX2Nv
bmZpZ19tb2RlKGh3ZGV2KSkKPiArCQlyZXR1cm4gMDsKPiArCj4gKwlyZXQgPSB3YWl0X2V2ZW50
X2ludGVycnVwdGlibGVfdGltZW91dChtYWxpZHAtPndxLAo+ICsJCQlhdG9taWNfcmVhZCgmbWFs
aWRwLT5jb25maWdfdmFsaWQpID09IDEsCj4gKwkJCW1zZWNzX3RvX2ppZmZpZXMoTUFMSURQX0NP
TkZfVkFMSURfVElNRU9VVCkpOwo+ICsKPiArCXJldHVybiAocmV0ID4gMCkgPyAwIDogLUVUSU1F
RE9VVDsKPiArfQo+ICsKPiArc3RhdGljIHZvaWQgbWFsaWRwX291dHB1dF9wb2xsX2NoYW5nZWQo
c3RydWN0IGRybV9kZXZpY2UgKmRybSkKPiArewo+ICsJc3RydWN0IG1hbGlkcF9kcm0gKm1hbGlk
cCA9IGRybS0+ZGV2X3ByaXZhdGU7Cj4gKwo+ICsJaWYgKG1hbGlkcC0+ZmJkZXYpCj4gKwkJZHJt
X2ZiZGV2X2NtYV9ob3RwbHVnX2V2ZW50KG1hbGlkcC0+ZmJkZXYpOwo+ICt9Cj4gKwo+ICtzdGF0
aWMgdm9pZCBtYWxpZHBfYXRvbWljX2NvbXBsZXRlKHN0cnVjdCBkcm1fZGV2aWNlICpkcm0sCj4g
KwkJCQkgICBzdHJ1Y3QgZHJtX2F0b21pY19zdGF0ZSAqb2xkX3N0YXRlKQo+ICt7Cj4gKwkvKiBU
b0RvOiB3YWl0X2Zvcl9mZW5jZXMoZHJtLCBvbGRfc3RhdGUpOyAqLwo+ICsKPiArCWRybV9hdG9t
aWNfaGVscGVyX2NvbW1pdF9tb2Rlc2V0X2Rpc2FibGVzKGRybSwgb2xkX3N0YXRlKTsKPiArCWRy
bV9hdG9taWNfaGVscGVyX2NvbW1pdF9wbGFuZXMoZHJtLCBvbGRfc3RhdGUsIGZhbHNlKTsKPiAr
CWRybV9hdG9taWNfaGVscGVyX2NvbW1pdF9tb2Rlc2V0X2VuYWJsZXMoZHJtLCBvbGRfc3RhdGUp
Owo+ICsKPiArCWRybV9hdG9taWNfaGVscGVyX3dhaXRfZm9yX3ZibGFua3MoZHJtLCBvbGRfc3Rh
dGUpOwo+ICsKPiArCWRybV9hdG9taWNfaGVscGVyX2NsZWFudXBfcGxhbmVzKGRybSwgb2xkX3N0
YXRlKTsKPiArCWRybV9hdG9taWNfc3RhdGVfZnJlZShvbGRfc3RhdGUpOwo+ICt9Cj4gKwo+ICtz
dGF0aWMgdm9pZCBtYWxpZHBfYXRvbWljX3dvcmsoc3RydWN0IHdvcmtfc3RydWN0ICp3b3JrKQo+
ICt7Cj4gKwlzdHJ1Y3QgbWFsaWRwX2RybSAqbWFsaWRwID0gY29udGFpbmVyX29mKHdvcmssIHN0
cnVjdCBtYWxpZHBfZHJtLAo+ICsJCQkJCQkgY29tbWl0LndvcmspOwo+ICsKPiArCW1hbGlkcF9h
dG9taWNfY29tcGxldGUobWFsaWRwLT5jb21taXQuc3RhdGUtPmRldiwKPiArCQkJICAgICAgIG1h
bGlkcC0+Y29tbWl0LnN0YXRlKTsKPiArfQo+ICsKPiArc3RhdGljIGludCBtYWxpZHBfYXRvbWlj
X2NvbW1pdChzdHJ1Y3QgZHJtX2RldmljZSAqZHJtLAo+ICsJCQkJc3RydWN0IGRybV9hdG9taWNf
c3RhdGUgKnN0YXRlLAo+ICsJCQkJYm9vbCBhc3luYykKPiArewo+ICsJc3RydWN0IG1hbGlkcF9k
cm0gKm1hbGlkcCA9IGRybS0+ZGV2X3ByaXZhdGU7Cj4gKwlpbnQgZXJyOwo+ICsKPiArCWVyciA9
IGRybV9hdG9taWNfaGVscGVyX3ByZXBhcmVfcGxhbmVzKGRybSwgc3RhdGUpOwo+ICsJaWYgKGVy
cikKPiArCQlyZXR1cm4gZXJyOwo+ICsKPiArCWlmIChhc3luYyAmJiAhbGlzdF9lbXB0eSgmbWFs
aWRwLT5jb21taXQud29yay5lbnRyeSkpIHsKPiArCQkvKiBwZW5kaW5nIGNvbW1pdHMgZm91bmQs
IGJhaWwgb3V0ICovCj4gKwkJcmV0dXJuIC1FQlVTWTsKPiArCX0KPiArCj4gKwltdXRleF9sb2Nr
KCZtYWxpZHAtPmNvbW1pdC5sb2NrKTsKPiArCWZsdXNoX3dvcmsoJm1hbGlkcC0+Y29tbWl0Lndv
cmspOwo+ICsKPiArCS8qCj4gKwkgKiBUaGUgcG9pbnQgb2Ygbm8gcmV0dXJuIGF3YWl0cyBoZXJl
LiBBZnRlciB0aGlzIHdlIGNvbW1pdAo+ICsJICogb24gc29mdHdhcmUgc2lkZSB0byBoYW5kbGUg
dGhlIG5ldyBzdGF0ZQo+ICsJICovCj4gKwlkcm1fYXRvbWljX2hlbHBlcl9zd2FwX3N0YXRlKGRy
bSwgc3RhdGUpOwo+ICsKPiArCW1hbGlkcC0+Y29tbWl0LnN0YXRlID0gc3RhdGU7Cj4gKwo+ICsJ
aWYgKGFzeW5jKQo+ICsJCXNjaGVkdWxlX3dvcmsoJm1hbGlkcC0+Y29tbWl0LndvcmspOwo+ICsJ
ZWxzZQo+ICsJCW1hbGlkcF9hdG9taWNfY29tcGxldGUoZHJtLCBzdGF0ZSk7Cj4gKwo+ICsJbXV0
ZXhfdW5sb2NrKCZtYWxpZHAtPmNvbW1pdC5sb2NrKTsKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+
ICtzdGF0aWMgY29uc3Qgc3RydWN0IGRybV9tb2RlX2NvbmZpZ19mdW5jcyBtYWxpZHBfbW9kZV9j
b25maWdfZnVuY3MgPSB7Cj4gKwkuZmJfY3JlYXRlID0gZHJtX2ZiX2NtYV9jcmVhdGUsCj4gKwku
b3V0cHV0X3BvbGxfY2hhbmdlZCA9IG1hbGlkcF9vdXRwdXRfcG9sbF9jaGFuZ2VkLAo+ICsJLmF0
b21pY19jaGVjayA9IGRybV9hdG9taWNfaGVscGVyX2NoZWNrLAo+ICsJLmF0b21pY19jb21taXQg
PSBtYWxpZHBfYXRvbWljX2NvbW1pdCwKPiArfTsKPiArCj4gK3N0YXRpYyBpbnQgbWFsaWRwX2Vu
YWJsZV92Ymxhbmsoc3RydWN0IGRybV9kZXZpY2UgKmRybSwgdW5zaWduZWQgaW50IGNydGMpCj4g
K3sKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCBtYWxpZHBfZGlzYWJsZV92
Ymxhbmsoc3RydWN0IGRybV9kZXZpY2UgKmRybSwgdW5zaWduZWQgaW50IHBpcGUpCj4gK3sKPiAr
fQo+ICsKPiArc3RhdGljIGludCBtYWxpZHBfaW5pdChzdHJ1Y3QgZHJtX2RldmljZSAqZHJtKQo+
ICt7Cj4gKwlpbnQgcmV0Owo+ICsJc3RydWN0IG1hbGlkcF9kcm0gKm1hbGlkcCA9IGRybS0+ZGV2
X3ByaXZhdGU7Cj4gKwlzdHJ1Y3QgbWFsaWRwX2h3X2RldmljZSAqaHdkZXYgPSBtYWxpZHAtPmRl
djsKPiArCj4gKwlkcm1fbW9kZV9jb25maWdfaW5pdChkcm0pOwo+ICsKPiArCWRybS0+bW9kZV9j
b25maWcubWluX3dpZHRoID0gaHdkZXYtPm1pbl9saW5lX3NpemU7Cj4gKwlkcm0tPm1vZGVfY29u
ZmlnLm1pbl9oZWlnaHQgPSBod2Rldi0+bWluX2xpbmVfc2l6ZTsKPiArCWRybS0+bW9kZV9jb25m
aWcubWF4X3dpZHRoID0gaHdkZXYtPm1heF9saW5lX3NpemU7Cj4gKwlkcm0tPm1vZGVfY29uZmln
Lm1heF9oZWlnaHQgPSBod2Rldi0+bWF4X2xpbmVfc2l6ZTsKPiArCWRybS0+bW9kZV9jb25maWcu
ZnVuY3MgPSAmbWFsaWRwX21vZGVfY29uZmlnX2Z1bmNzOwo+ICsKPiArCXJldCA9IG1hbGlkcF9k
ZV9wbGFuZXNfaW5pdChkcm0pOwo+ICsJaWYgKHJldCA8IDApIHsKPiArCQlEUk1fRVJST1IoIkZh
aWxlZCB0byBpbml0aWFsaXNlIHBsYW5lc1xuIik7Cj4gKwkJZ290byBwbGFuZV9pbml0X2ZhaWw7
Cj4gKwl9Cj4gKwo+ICsJcmV0ID0gbWFsaWRwX2NydGNfaW5pdChkcm0pOwo+ICsJaWYgKHJldCkg
ewo+ICsJCURSTV9FUlJPUigiRmFpbGVkIHRvIGluaXRpYWxpc2UgQ1JUQ1xuIik7Cj4gKwkJZ290
byBjcnRjX2luaXRfZmFpbDsKPiArCX0KPiArCj4gKwlyZXR1cm4gMDsKPiArCj4gK2NydGNfaW5p
dF9mYWlsOgo+ICsJbWFsaWRwX2RlX3BsYW5lc19kZXN0cm95KGRybSk7Cj4gK3BsYW5lX2luaXRf
ZmFpbDoKPiArCWRybV9tb2RlX2NvbmZpZ19jbGVhbnVwKGRybSk7Cj4gKwo+ICsJcmV0dXJuIHJl
dDsKPiArfQo+ICsKPiArc3RhdGljIGludCBtYWxpZHBfaXJxX2luaXQoc3RydWN0IHBsYXRmb3Jt
X2RldmljZSAqcGRldikKPiArewo+ICsJaW50IGlycV9kZSwgaXJxX3NlLCByZXQgPSAwOwo+ICsJ
c3RydWN0IGRybV9kZXZpY2UgKmRybSA9IGRldl9nZXRfZHJ2ZGF0YSgmcGRldi0+ZGV2KTsKPiAr
Cj4gKwkvKiBmZXRjaCB0aGUgaW50ZXJydXB0cyBmcm9tIERUICovCj4gKwlpcnFfZGUgPSBwbGF0
Zm9ybV9nZXRfaXJxX2J5bmFtZShwZGV2LCAiREUiKTsKPiArCWlmIChpcnFfZGUgPCAwKSB7Cj4g
KwkJRFJNX0VSUk9SKCJubyAnREUnIElSUSBzcGVjaWZpZWQhXG4iKTsKPiArCQlyZXR1cm4gaXJx
X2RlOwo+ICsJfQo+ICsJaXJxX3NlID0gcGxhdGZvcm1fZ2V0X2lycV9ieW5hbWUocGRldiwgIlNF
Iik7Cj4gKwlpZiAoaXJxX3NlIDwgMCkgewo+ICsJCURSTV9FUlJPUigibm8gJ1NFJyBJUlEgc3Bl
Y2lmaWVkIVxuIik7Cj4gKwkJcmV0dXJuIGlycV9zZTsKPiArCX0KPiArCj4gKwlyZXQgPSBtYWxp
ZHBfZGVfaXJxX2luaXQoZHJtLCBpcnFfZGUpOwo+ICsJaWYgKHJldCkKPiArCQlyZXR1cm4gcmV0
Owo+ICsKPiArCXJldCA9IG1hbGlkcF9zZV9pcnFfaW5pdChkcm0sIGlycV9zZSk7Cj4gKwlpZiAo
cmV0KSB7Cj4gKwkJbWFsaWRwX2RlX2lycV9jbGVhbnVwKGRybSk7Cj4gKwkJcmV0dXJuIHJldDsK
PiArCX0KPiArCj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiArc3RhdGljIHZvaWQgbWFsaWRwX2xh
c3RjbG9zZShzdHJ1Y3QgZHJtX2RldmljZSAqZHJtKQo+ICt7Cj4gKwlzdHJ1Y3QgbWFsaWRwX2Ry
bSAqbWFsaWRwID0gZHJtLT5kZXZfcHJpdmF0ZTsKPiArCj4gKwlkcm1fZmJkZXZfY21hX3Jlc3Rv
cmVfbW9kZShtYWxpZHAtPmZiZGV2KTsKPiArfQo+ICsKPiArc3RhdGljIGNvbnN0IHN0cnVjdCBm
aWxlX29wZXJhdGlvbnMgZm9wcyA9IHsKPiArCS5vd25lciA9IFRISVNfTU9EVUxFLAo+ICsJLm9w
ZW4gPSBkcm1fb3BlbiwKPiArCS5yZWxlYXNlID0gZHJtX3JlbGVhc2UsCj4gKwkudW5sb2NrZWRf
aW9jdGwgPSBkcm1faW9jdGwsCj4gKyNpZmRlZiBDT05GSUdfQ09NUEFUCj4gKwkuY29tcGF0X2lv
Y3RsID0gZHJtX2NvbXBhdF9pb2N0bCwKPiArI2VuZGlmCj4gKwkucG9sbCA9IGRybV9wb2xsLAo+
ICsJLnJlYWQgPSBkcm1fcmVhZCwKPiArCS5sbHNlZWsgPSBub29wX2xsc2VlaywKPiArCS5tbWFw
ID0gZHJtX2dlbV9jbWFfbW1hcCwKPiArfTsKPiArCj4gK3N0YXRpYyBzdHJ1Y3QgZHJtX2RyaXZl
ciBtYWxpZHBfZHJpdmVyID0gewo+ICsJLmRyaXZlcl9mZWF0dXJlcyA9IERSSVZFUl9HRU0gfCBE
UklWRVJfTU9ERVNFVCB8IERSSVZFUl9BVE9NSUMgfAo+ICsJCQkgICBEUklWRVJfUFJJTUUsCj4g
KwkubGFzdGNsb3NlID0gbWFsaWRwX2xhc3RjbG9zZSwKPiArCS5nZXRfdmJsYW5rX2NvdW50ZXIg
PSBkcm1fdmJsYW5rX25vX2h3X2NvdW50ZXIsCj4gKwkuZW5hYmxlX3ZibGFuayA9IG1hbGlkcF9l
bmFibGVfdmJsYW5rLAo+ICsJLmRpc2FibGVfdmJsYW5rID0gbWFsaWRwX2Rpc2FibGVfdmJsYW5r
LAo+ICsJLmdlbV9mcmVlX29iamVjdCA9IGRybV9nZW1fY21hX2ZyZWVfb2JqZWN0LAo+ICsJLmdl
bV92bV9vcHMgPSAmZHJtX2dlbV9jbWFfdm1fb3BzLAo+ICsJLmR1bWJfY3JlYXRlID0gZHJtX2dl
bV9jbWFfZHVtYl9jcmVhdGUsCj4gKwkuZHVtYl9tYXBfb2Zmc2V0ID0gZHJtX2dlbV9jbWFfZHVt
Yl9tYXBfb2Zmc2V0LAo+ICsJLmR1bWJfZGVzdHJveSA9IGRybV9nZW1fZHVtYl9kZXN0cm95LAo+
ICsJLnByaW1lX2hhbmRsZV90b19mZCA9IGRybV9nZW1fcHJpbWVfaGFuZGxlX3RvX2ZkLAo+ICsJ
LnByaW1lX2ZkX3RvX2hhbmRsZSA9IGRybV9nZW1fcHJpbWVfZmRfdG9faGFuZGxlLAo+ICsJLmdl
bV9wcmltZV9leHBvcnQgPSBkcm1fZ2VtX3ByaW1lX2V4cG9ydCwKPiArCS5nZW1fcHJpbWVfaW1w
b3J0ID0gZHJtX2dlbV9wcmltZV9pbXBvcnQsCj4gKwkuZ2VtX3ByaW1lX2dldF9zZ190YWJsZSA9
IGRybV9nZW1fY21hX3ByaW1lX2dldF9zZ190YWJsZSwKPiArCS5nZW1fcHJpbWVfaW1wb3J0X3Nn
X3RhYmxlID0gZHJtX2dlbV9jbWFfcHJpbWVfaW1wb3J0X3NnX3RhYmxlLAo+ICsJLmdlbV9wcmlt
ZV92bWFwID0gZHJtX2dlbV9jbWFfcHJpbWVfdm1hcCwKPiArCS5nZW1fcHJpbWVfdnVubWFwID0g
ZHJtX2dlbV9jbWFfcHJpbWVfdnVubWFwLAo+ICsJLmdlbV9wcmltZV9tbWFwID0gZHJtX2dlbV9j
bWFfcHJpbWVfbW1hcCwKPiArCS5mb3BzID0gJmZvcHMsCj4gKwkubmFtZSA9ICJtYWxpLWRwIiwK
PiArCS5kZXNjID0gIkFSTSBNYWxpIERpc3BsYXkgUHJvY2Vzc29yIGRyaXZlciIsCj4gKwkuZGF0
ZSA9ICIyMDE2MDEwNiIsCj4gKwkubWFqb3IgPSAxLAo+ICsJLm1pbm9yID0gMCwKPiArfTsKPiAr
Cj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkICBtYWxpZHBfZHJtX29mX21hdGNo
W10gPSB7Cj4gKwl7Cj4gKwkJLmNvbXBhdGlibGUgPSAiYXJtLG1hbGktZHA1MDAiLAo+ICsJCS5k
YXRhID0gJm1hbGlkcF9kZXZpY2VbTUFMSURQXzUwMF0KPiArCX0sCj4gKwl7Cj4gKwkJLmNvbXBh
dGlibGUgPSAiYXJtLG1hbGktZHA1NTAiLAo+ICsJCS5kYXRhID0gJm1hbGlkcF9kZXZpY2VbTUFM
SURQXzU1MF0KPiArCX0sCj4gKwl7Cj4gKwkJLmNvbXBhdGlibGUgPSAiYXJtLG1hbGktZHA2NTAi
LAo+ICsJCS5kYXRhID0gJm1hbGlkcF9kZXZpY2VbTUFMSURQXzY1MF0KPiArCX0sCj4gKwl7fSwK
PiArfTsKPiArTU9EVUxFX0RFVklDRV9UQUJMRShvZiwgbWFsaWRwX2RybV9vZl9tYXRjaCk7Cj4g
Kwo+ICsjZGVmaW5lIE1BWF9PVVRQVVRfQ0hBTk5FTFMJMwo+ICsKPiArc3RhdGljIGludCBtYWxp
ZHBfYmluZChzdHJ1Y3QgZGV2aWNlICpkZXYpCj4gK3sKPiArCXN0cnVjdCByZXNvdXJjZSAqcmVz
Owo+ICsJc3RydWN0IGRybV9kZXZpY2UgKmRybTsKPiArCXN0cnVjdCBtYWxpZHBfZHJtICptYWxp
ZHA7Cj4gKwlzdHJ1Y3QgbWFsaWRwX2h3X2RldmljZSAqaHdkZXY7Cj4gKwlzdHJ1Y3QgcGxhdGZv
cm1fZGV2aWNlICpwZGV2ID0gdG9fcGxhdGZvcm1fZGV2aWNlKGRldik7Cj4gKwkvKiBudW1iZXIg
b2YgbGluZXMgZm9yIHRoZSBSLCBHIGFuZCBCIG91dHB1dCAqLwo+ICsJdTggb3V0cHV0X3dpZHRo
W01BWF9PVVRQVVRfQ0hBTk5FTFNdOwo+ICsJaW50IHJldCA9IDAsIGk7Cj4gKwl1MzIgdmVyc2lv
biwgb3V0X2RlcHRoID0gMDsKPiArCj4gKwltYWxpZHAgPSBkZXZtX2t6YWxsb2MoZGV2LCBzaXpl
b2YoKm1hbGlkcCksIEdGUF9LRVJORUwpOwo+ICsJaWYgKCFtYWxpZHApCj4gKwkJcmV0dXJuIC1F
Tk9NRU07Cj4gKwo+ICsJaHdkZXYgPSBkZXZtX2t6YWxsb2MoZGV2LCBzaXplb2YoKmh3ZGV2KSwg
R0ZQX0tFUk5FTCk7Cj4gKwlpZiAoIWh3ZGV2KQo+ICsJCXJldHVybiAtRU5PTUVNOwo+ICsKPiAr
CS8qCj4gKwkgKiBjb3B5IHRoZSBhc3NvY2lhdGVkIGRhdGEgZnJvbSBtYWxpZHBfZHJtX29mX21h
dGNoIHRvIGF2b2lkCj4gKwkgKiBoYXZpbmcgdG8ga2VlcCBhIHJlZmVyZW5jZSB0byB0aGUgT0Yg
bm9kZSBhZnRlciBiaW5kaW5nCj4gKwkgKi8KPiArCW1lbWNweShod2Rldiwgb2ZfZGV2aWNlX2dl
dF9tYXRjaF9kYXRhKGRldiksIHNpemVvZigqaHdkZXYpKTsKPiArCW1hbGlkcC0+ZGV2ID0gaHdk
ZXY7Cj4gKwo+ICsJSU5JVF9MSVNUX0hFQUQoJm1hbGlkcC0+ZXZlbnRfbGlzdCk7Cj4gKwo+ICsJ
cmVzID0gcGxhdGZvcm1fZ2V0X3Jlc291cmNlKHBkZXYsIElPUkVTT1VSQ0VfTUVNLCAwKTsKPiAr
CWh3ZGV2LT5yZWdzID0gZGV2bV9pb3JlbWFwX3Jlc291cmNlKGRldiwgcmVzKTsKPiArCWlmIChJ
U19FUlIoaHdkZXYtPnJlZ3MpKSB7Cj4gKwkJRFJNX0VSUk9SKCJGYWlsZWQgdG8gbWFwIGNvbnRy
b2wgcmVnaXN0ZXJzIGFyZWFcbiIpOwo+ICsJCXJldHVybiBQVFJfRVJSKGh3ZGV2LT5yZWdzKTsK
PiArCX0KPiArCj4gKwlod2Rldi0+cGNsayA9IGRldm1fY2xrX2dldChkZXYsICJwY2xrIik7Cj4g
KwlpZiAoSVNfRVJSKGh3ZGV2LT5wY2xrKSkKPiArCQlyZXR1cm4gUFRSX0VSUihod2Rldi0+cGNs
ayk7Cj4gKwo+ICsJaHdkZXYtPmFjbGsgPSBkZXZtX2Nsa19nZXQoZGV2LCAiYWNsayIpOwo+ICsJ
aWYgKElTX0VSUihod2Rldi0+YWNsaykpCj4gKwkJcmV0dXJuIFBUUl9FUlIoaHdkZXYtPmFjbGsp
Owo+ICsKPiArCWh3ZGV2LT5tY2xrID0gZGV2bV9jbGtfZ2V0KGRldiwgIm1jbGsiKTsKPiArCWlm
IChJU19FUlIoaHdkZXYtPm1jbGspKQo+ICsJCXJldHVybiBQVFJfRVJSKGh3ZGV2LT5tY2xrKTsK
PiArCj4gKwlod2Rldi0+cHhsY2xrID0gZGV2bV9jbGtfZ2V0KGRldiwgInB4bGNsayIpOwo+ICsJ
aWYgKElTX0VSUihod2Rldi0+cHhsY2xrKSkKPiArCQlyZXR1cm4gUFRSX0VSUihod2Rldi0+cHhs
Y2xrKTsKPiArCj4gKwkvKiBHZXQgdGhlIG9wdGlvbmFsIGZyYW1lYnVmZmVyIG1lbW9yeSByZXNv
dXJjZSAqLwo+ICsJcmV0ID0gb2ZfcmVzZXJ2ZWRfbWVtX2RldmljZV9pbml0KGRldik7Cj4gKwlp
ZiAocmV0ICYmIHJldCAhPSAtRU5PREVWKQo+ICsJCXJldHVybiByZXQ7Cj4gKwo+ICsJZHJtID0g
ZHJtX2Rldl9hbGxvYygmbWFsaWRwX2RyaXZlciwgZGV2KTsKPiArCWlmICghZHJtKSB7Cj4gKwkJ
cmV0ID0gLUVOT01FTTsKPiArCQlnb3RvIGFsbG9jX2ZhaWw7Cj4gKwl9Cj4gKwo+ICsJLyogRW5h
YmxlIEFQQiBjbG9jayBpbiBvcmRlciB0byBnZXQgYWNjZXNzIHRvIHRoZSByZWdpc3RlcnMgKi8K
PiArCWNsa19wcmVwYXJlX2VuYWJsZShod2Rldi0+cGNsayk7Cj4gKwkvKgo+ICsJICogRW5hYmxl
IEFYSSBjbG9jayBhbmQgbWFpbiBjbG9jayBzbyB0aGF0IHByZWZldGNoIGNhbiBzdGFydCBvbmNl
Cj4gKwkgKiB0aGUgcmVnaXN0ZXJzIGFyZSBzZXQKPiArCSAqLwo+ICsJY2xrX3ByZXBhcmVfZW5h
YmxlKGh3ZGV2LT5hY2xrKTsKPiArCWNsa19wcmVwYXJlX2VuYWJsZShod2Rldi0+bWNsayk7Cj4g
Kwo+ICsJcmV0ID0gaHdkZXYtPnF1ZXJ5X2h3KGh3ZGV2KTsKPiArCWlmIChyZXQpIHsKPiArCQlE
Uk1fRVJST1IoIkludmFsaWQgSFcgY29uZmlndXJhdGlvblxuIik7Cj4gKwkJZ290byBxdWVyeV9o
d19mYWlsOwo+ICsJfQo+ICsKPiArCXZlcnNpb24gPSBtYWxpZHBfaHdfcmVhZChod2RldiwgaHdk
ZXYtPm1hcC5kY19iYXNlICsgTUFMSURQX0RFX0NPUkVfSUQpOwo+ICsJRFJNX0lORk8oImZvdW5k
IEFSTSBNYWxpLURQJTN4IHZlcnNpb24gciVkcCVkXG4iLCB2ZXJzaW9uID4+IDE2LAo+ICsJCSAo
dmVyc2lvbiA+PiAxMikgJiAweGYsICh2ZXJzaW9uID4+IDgpICYgMHhmKTsKPiArCj4gKwkvKiBz
ZXQgdGhlIG51bWJlciBvZiBsaW5lcyB1c2VkIGZvciBvdXRwdXQgb2YgUkdCIGRhdGEgKi8KPiAr
CXJldCA9IG9mX3Byb3BlcnR5X3JlYWRfdThfYXJyYXkoZGV2LT5vZl9ub2RlLAo+ICsJCQkJCSJh
cm0sbWFsaWRwLW91dHB1dC1wb3J0LWxpbmVzIiwKPiArCQkJCQlvdXRwdXRfd2lkdGgsIE1BWF9P
VVRQVVRfQ0hBTk5FTFMpOwo+ICsJaWYgKHJldCkKPiArCQlnb3RvIHF1ZXJ5X2h3X2ZhaWw7Cj4g
Kwo+ICsJZm9yIChpID0gMDsgaSA8IE1BWF9PVVRQVVRfQ0hBTk5FTFM7IGkrKykKPiArCQlvdXRf
ZGVwdGggPSAob3V0X2RlcHRoIDw8IDgpIHwgKG91dHB1dF93aWR0aFtpXSAmIDB4Zik7Cj4gKwlt
YWxpZHBfaHdfd3JpdGUoaHdkZXYsIG91dF9kZXB0aCwgaHdkZXYtPm1hcC5vdXRfZGVwdGhfYmFz
ZSk7Cj4gKwo+ICsJZHJtLT5kZXZfcHJpdmF0ZSA9IG1hbGlkcDsKPiArCWRldl9zZXRfZHJ2ZGF0
YShkZXYsIGRybSk7Cj4gKwlhdG9taWNfc2V0KCZtYWxpZHAtPmNvbmZpZ192YWxpZCwgMCk7Cj4g
Kwlpbml0X3dhaXRxdWV1ZV9oZWFkKCZtYWxpZHAtPndxKTsKPiArCj4gKwltdXRleF9pbml0KCZt
YWxpZHAtPmNvbW1pdC5sb2NrKTsKPiArCUlOSVRfV09SSygmbWFsaWRwLT5jb21taXQud29yaywg
bWFsaWRwX2F0b21pY193b3JrKTsKPiArCj4gKwlyZXQgPSBtYWxpZHBfaW5pdChkcm0pOwo+ICsJ
aWYgKHJldCA8IDApCj4gKwkJZ290byBpbml0X2ZhaWw7Cj4gKwo+ICsJcmV0ID0gZHJtX2Rldl9y
ZWdpc3Rlcihkcm0sIDApOwo+ICsJaWYgKHJldCkKPiArCQlnb3RvIHJlZ2lzdGVyX2ZhaWw7Cj4g
Kwo+ICsJLyogU2V0IHRoZSBDUlRDJ3MgcG9ydCBzbyB0aGF0IHRoZSBlbmNvZGVyIGNvbXBvbmVu
dCBjYW4gZmluZCBpdCAqLwo+ICsJbWFsaWRwLT5jcnRjLnBvcnQgPSBvZl9ncmFwaF9nZXRfbmV4
dF9lbmRwb2ludChkZXYtPm9mX25vZGUsIE5VTEwpOwo+ICsKPiArCXJldCA9IGNvbXBvbmVudF9i
aW5kX2FsbChkZXYsIGRybSk7Cj4gKwlvZl9ub2RlX3B1dChtYWxpZHAtPmNydGMucG9ydCk7Cj4g
Kwo+ICsJaWYgKHJldCkgewo+ICsJCURSTV9FUlJPUigiRmFpbGVkIHRvIGJpbmQgYWxsIGNvbXBv
bmVudHNcbiIpOwo+ICsJCWdvdG8gYmluZF9mYWlsOwo+ICsJfQo+ICsKPiArCXJldCA9IGRybV92
YmxhbmtfaW5pdChkcm0sIGRybS0+bW9kZV9jb25maWcubnVtX2NydGMpOwo+ICsJaWYgKHJldCA8
IDApIHsKPiArCQlEUk1fRVJST1IoImZhaWxlZCB0byBpbml0aWFsaXNlIHZibGFua1xuIik7Cj4g
KwkJZ290byB2YmxhbmtfZmFpbDsKPiArCX0KPiArCWRybS0+dmJsYW5rX2Rpc2FibGVfYWxsb3dl
ZCA9IHRydWU7Cj4gKwo+ICsJcmV0ID0gbWFsaWRwX2lycV9pbml0KHBkZXYpOwo+ICsJaWYgKHJl
dCA8IDApCj4gKwkJZ290byBpcnFfaW5pdF9mYWlsOwo+ICsKPiArCWRybV9tb2RlX2NvbmZpZ19y
ZXNldChkcm0pOwo+ICsKPiArCWRybV9oZWxwZXJfZGlzYWJsZV91bnVzZWRfZnVuY3Rpb25zKGRy
bSk7Cj4gKwltYWxpZHAtPmZiZGV2ID0gZHJtX2ZiZGV2X2NtYV9pbml0KGRybSwgMzIsIGRybS0+
bW9kZV9jb25maWcubnVtX2NydGMsCj4gKwkJCQkJICAgZHJtLT5tb2RlX2NvbmZpZy5udW1fY29u
bmVjdG9yKTsKPiArCj4gKwlpZiAoSVNfRVJSKG1hbGlkcC0+ZmJkZXYpKSB7Cj4gKwkJcmV0ID0g
UFRSX0VSUihtYWxpZHAtPmZiZGV2KTsKPiArCQltYWxpZHAtPmZiZGV2ID0gTlVMTDsKPiArCQln
b3RvIGZiZGV2X2ZhaWw7Cj4gKwl9Cj4gKwo+ICsJZHJtX2ttc19oZWxwZXJfcG9sbF9pbml0KGRy
bSk7Cj4gKwlyZXR1cm4gMDsKPiArCj4gK2ZiZGV2X2ZhaWw6Cj4gKwltYWxpZHBfc2VfaXJxX2Ns
ZWFudXAoZHJtKTsKPiArCW1hbGlkcF9kZV9pcnFfY2xlYW51cChkcm0pOwo+ICtpcnFfaW5pdF9m
YWlsOgo+ICsJZHJtX3ZibGFua19jbGVhbnVwKGRybSk7Cj4gK3ZibGFua19mYWlsOgo+ICsJY29t
cG9uZW50X3VuYmluZF9hbGwoZGV2LCBkcm0pOwo+ICtiaW5kX2ZhaWw6Cj4gKwlkcm1fZGV2X3Vu
cmVnaXN0ZXIoZHJtKTsKPiArcmVnaXN0ZXJfZmFpbDoKPiArCW1hbGlkcF9kZV9wbGFuZXNfZGVz
dHJveShkcm0pOwo+ICsJZHJtX21vZGVfY29uZmlnX2NsZWFudXAoZHJtKTsKPiAraW5pdF9mYWls
Ogo+ICsJZHJtLT5kZXZfcHJpdmF0ZSA9IE5VTEw7Cj4gKwlkZXZfc2V0X2RydmRhdGEoZGV2LCBO
VUxMKTsKPiArcXVlcnlfaHdfZmFpbDoKPiArCWNsa19kaXNhYmxlX3VucHJlcGFyZShod2Rldi0+
bWNsayk7Cj4gKwljbGtfZGlzYWJsZV91bnByZXBhcmUoaHdkZXYtPmFjbGspOwo+ICsJY2xrX2Rp
c2FibGVfdW5wcmVwYXJlKGh3ZGV2LT5wY2xrKTsKPiArCWRybV9kZXZfdW5yZWYoZHJtKTsKPiAr
YWxsb2NfZmFpbDoKPiArCW9mX3Jlc2VydmVkX21lbV9kZXZpY2VfcmVsZWFzZShkZXYpOwo+ICsK
PiArCXJldHVybiByZXQ7Cj4gK30KPiArCj4gK3N0YXRpYyB2b2lkIG1hbGlkcF91bmJpbmQoc3Ry
dWN0IGRldmljZSAqZGV2KQo+ICt7Cj4gKwlzdHJ1Y3QgZHJtX2RldmljZSAqZHJtID0gZGV2X2dl
dF9kcnZkYXRhKGRldik7Cj4gKwlzdHJ1Y3QgbWFsaWRwX2RybSAqbWFsaWRwID0gZHJtLT5kZXZf
cHJpdmF0ZTsKPiArCXN0cnVjdCBtYWxpZHBfaHdfZGV2aWNlICpod2RldiA9IG1hbGlkcC0+ZGV2
Owo+ICsKPiArCWlmIChtYWxpZHAtPmZiZGV2KSB7Cj4gKwkJZHJtX2ZiZGV2X2NtYV9maW5pKG1h
bGlkcC0+ZmJkZXYpOwo+ICsJCW1hbGlkcC0+ZmJkZXYgPSBOVUxMOwo+ICsJfQo+ICsJZHJtX2tt
c19oZWxwZXJfcG9sbF9maW5pKGRybSk7Cj4gKwltYWxpZHBfc2VfaXJxX2NsZWFudXAoZHJtKTsK
PiArCW1hbGlkcF9kZV9pcnFfY2xlYW51cChkcm0pOwo+ICsJZHJtX3ZibGFua19jbGVhbnVwKGRy
bSk7Cj4gKwljb21wb25lbnRfdW5iaW5kX2FsbChkZXYsIGRybSk7Cj4gKwlkcm1fZGV2X3VucmVn
aXN0ZXIoZHJtKTsKPiArCW1hbGlkcF9kZV9wbGFuZXNfZGVzdHJveShkcm0pOwo+ICsJZHJtX21v
ZGVfY29uZmlnX2NsZWFudXAoZHJtKTsKPiArCWRybS0+ZGV2X3ByaXZhdGUgPSBOVUxMOwo+ICsJ
ZGV2X3NldF9kcnZkYXRhKGRldiwgTlVMTCk7Cj4gKwljbGtfZGlzYWJsZV91bnByZXBhcmUoaHdk
ZXYtPm1jbGspOwo+ICsJY2xrX2Rpc2FibGVfdW5wcmVwYXJlKGh3ZGV2LT5hY2xrKTsKPiArCWNs
a19kaXNhYmxlX3VucHJlcGFyZShod2Rldi0+cGNsayk7Cj4gKwlkcm1fZGV2X3VucmVmKGRybSk7
Cj4gKwlvZl9yZXNlcnZlZF9tZW1fZGV2aWNlX3JlbGVhc2UoZGV2KTsKPiArfQo+ICsKPiArc3Rh
dGljIGNvbnN0IHN0cnVjdCBjb21wb25lbnRfbWFzdGVyX29wcyBtYWxpZHBfbWFzdGVyX29wcyA9
IHsKPiArCS5iaW5kID0gbWFsaWRwX2JpbmQsCj4gKwkudW5iaW5kID0gbWFsaWRwX3VuYmluZCwK
PiArfTsKPiArCj4gK3N0YXRpYyBpbnQgbWFsaWRwX2NvbXBhcmVfZGV2KHN0cnVjdCBkZXZpY2Ug
KmRldiwgdm9pZCAqZGF0YSkKPiArewo+ICsJc3RydWN0IGRldmljZV9ub2RlICpucCA9IGRhdGE7
Cj4gKwo+ICsJcmV0dXJuIGRldi0+b2Zfbm9kZSA9PSBucDsKPiArfQo+ICsKPiArc3RhdGljIGlu
dCBtYWxpZHBfcGxhdGZvcm1fcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKPiAr
ewo+ICsJc3RydWN0IGRldmljZV9ub2RlICpwb3J0LCAqZXA7Cj4gKwlzdHJ1Y3QgY29tcG9uZW50
X21hdGNoICptYXRjaCA9IE5VTEw7Cj4gKwo+ICsJaWYgKCFwZGV2LT5kZXYub2Zfbm9kZSkKPiAr
CQlyZXR1cm4gLUVOT0RFVjsKPiArCj4gKwkvKiB0aGVyZSBpcyBvbmx5IG9uZSBvdXRwdXQgcG9y
dCBpbnNpZGUgZWFjaCBkZXZpY2UsIGZpbmQgaXQgKi8KPiArCWVwID0gb2ZfZ3JhcGhfZ2V0X25l
eHRfZW5kcG9pbnQocGRldi0+ZGV2Lm9mX25vZGUsIE5VTEwpOwo+ICsJaWYgKCFlcCkKPiArCQly
ZXR1cm4gLUVOT0RFVjsKPiArCj4gKwlpZiAoIW9mX2RldmljZV9pc19hdmFpbGFibGUoZXApKSB7
Cj4gKwkJb2Zfbm9kZV9wdXQoZXApOwo+ICsJCXJldHVybiAtRU5PREVWOwo+ICsJfQo+ICsKPiAr
CS8qIGFkZCB0aGUgcmVtb3RlIGVuY29kZXIgcG9ydCBhcyBjb21wb25lbnQgKi8KPiArCXBvcnQg
PSBvZl9ncmFwaF9nZXRfcmVtb3RlX3BvcnRfcGFyZW50KGVwKTsKPiArCW9mX25vZGVfcHV0KGVw
KTsKPiArCWlmICghcG9ydCB8fCAhb2ZfZGV2aWNlX2lzX2F2YWlsYWJsZShwb3J0KSkgewo+ICsJ
CW9mX25vZGVfcHV0KHBvcnQpOwo+ICsJCXJldHVybiAtRUFHQUlOOwo+ICsJfQo+ICsKPiArCWNv
bXBvbmVudF9tYXRjaF9hZGQoJnBkZXYtPmRldiwgJm1hdGNoLCBtYWxpZHBfY29tcGFyZV9kZXYs
IHBvcnQpOwo+ICsJcmV0dXJuIGNvbXBvbmVudF9tYXN0ZXJfYWRkX3dpdGhfbWF0Y2goJnBkZXYt
PmRldiwgJm1hbGlkcF9tYXN0ZXJfb3BzLAo+ICsJCQkJCSAgICAgICBtYXRjaCk7Cj4gK30KPiAr
Cj4gK3N0YXRpYyBpbnQgbWFsaWRwX3BsYXRmb3JtX3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2
aWNlICpwZGV2KQo+ICt7Cj4gKwljb21wb25lbnRfbWFzdGVyX2RlbCgmcGRldi0+ZGV2LCAmbWFs
aWRwX21hc3Rlcl9vcHMpOwo+ICsJcmV0dXJuIDA7Cj4gK30KPiArCj4gK3N0YXRpYyBzdHJ1Y3Qg
cGxhdGZvcm1fZHJpdmVyIG1hbGlkcF9wbGF0Zm9ybV9kcml2ZXIgPSB7Cj4gKwkucHJvYmUJCT0g
bWFsaWRwX3BsYXRmb3JtX3Byb2JlLAo+ICsJLnJlbW92ZQkJPSBtYWxpZHBfcGxhdGZvcm1fcmVt
b3ZlLAo+ICsJLmRyaXZlcgk9IHsKPiArCQkubmFtZSA9ICJtYWxpLWRwIiwKPiArCQkub2ZfbWF0
Y2hfdGFibGUJPSBtYWxpZHBfZHJtX29mX21hdGNoLAo+ICsJfSwKPiArfTsKPiArCj4gK21vZHVs
ZV9wbGF0Zm9ybV9kcml2ZXIobWFsaWRwX3BsYXRmb3JtX2RyaXZlcik7Cj4gKwo+ICtNT0RVTEVf
QVVUSE9SKCJMaXZpdSBEdWRhdSA8TGl2aXUuRHVkYXVAYXJtLmNvbT4iKTsKPiArTU9EVUxFX0RF
U0NSSVBUSU9OKCJBUk0gTWFsaSBEUCBEUk0gZHJpdmVyIik7Cj4gK01PRFVMRV9MSUNFTlNFKCJH
UEwgdjIiKTsKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2FybS9tYWxpZHBfZHJ2Lmgg
Yi9kcml2ZXJzL2dwdS9kcm0vYXJtL21hbGlkcF9kcnYuaAo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0
Cj4gaW5kZXggMDAwMDAwMC4uZWZmZDNiZQo+IC0tLSAvZGV2L251bGwKPiArKysgYi9kcml2ZXJz
L2dwdS9kcm0vYXJtL21hbGlkcF9kcnYuaAo+IEBAIC0wLDAgKzEsNTQgQEAKPiArLyoKPiArICog
KEMpIENPUFlSSUdIVCAyMDE2IEFSTSBMaW1pdGVkLiBBbGwgcmlnaHRzIHJlc2VydmVkLgo+ICsg
KiBBdXRob3I6IExpdml1IER1ZGF1IDxMaXZpdS5EdWRhdUBhcm0uY29tPgo+ICsgKgo+ICsgKiBU
aGlzIHByb2dyYW0gaXMgZnJlZSBzb2Z0d2FyZSBhbmQgaXMgcHJvdmlkZWQgdG8geW91IHVuZGVy
IHRoZSB0ZXJtcyBvZiB0aGUKPiArICogR05VIEdlbmVyYWwgUHVibGljIExpY2Vuc2UgdmVyc2lv
biAyIGFzIHB1Ymxpc2hlZCBieSB0aGUgRnJlZSBTb2Z0d2FyZQo+ICsgKiBGb3VuZGF0aW9uLCBh
bmQgYW55IHVzZSBieSB5b3Ugb2YgdGhpcyBwcm9ncmFtIGlzIHN1YmplY3QgdG8gdGhlIHRlcm1z
Cj4gKyAqIG9mIHN1Y2ggR05VIGxpY2VuY2UuCj4gKyAqCj4gKyAqIEFSTSBNYWxpIERQNTAwL0RQ
NTUwL0RQNjUwIEtNUy9EUk0gZHJpdmVyIHN0cnVjdHVyZXMKPiArICovCj4gKwo+ICsjaWZuZGVm
IF9fTUFMSURQX0RSVl9IX18KPiArI2RlZmluZSBfX01BTElEUF9EUlZfSF9fCj4gKwo+ICsjaW5j
bHVkZSA8bGludXgvbXV0ZXguaD4KPiArI2luY2x1ZGUgPGxpbnV4L3dhaXQuaD4KPiArI2luY2x1
ZGUgIm1hbGlkcF9ody5oIgo+ICsKPiArc3RydWN0IG1hbGlkcF9kcm0gewo+ICsJc3RydWN0IG1h
bGlkcF9od19kZXZpY2UgKmRldjsKPiArCXN0cnVjdCBkcm1fZmJkZXZfY21hICpmYmRldjsKPiAr
CXN0cnVjdCBsaXN0X2hlYWQgZXZlbnRfbGlzdDsKPiArCXN0cnVjdCBkcm1fY3J0YyBjcnRjOwo+
ICsJd2FpdF9xdWV1ZV9oZWFkX3Qgd3E7Cj4gKwlzdHJ1Y3Qgewo+ICsJCXN0cnVjdCBkcm1fYXRv
bWljX3N0YXRlICpzdGF0ZTsKPiArCQlzdHJ1Y3Qgd29ya19zdHJ1Y3Qgd29yazsKPiArCQlzdHJ1
Y3QgbXV0ZXggbG9jazsKPiArCX0gY29tbWl0Owo+ICsJYXRvbWljX3QgY29uZmlnX3ZhbGlkOwo+
ICt9Owo+ICsKPiArI2RlZmluZSBjcnRjX3RvX21hbGlkcF9kZXZpY2UoeCkgY29udGFpbmVyX29m
KHgsIHN0cnVjdCBtYWxpZHBfZHJtLCBjcnRjKQo+ICsKPiArc3RydWN0IG1hbGlkcF9wbGFuZSB7
Cj4gKwlzdHJ1Y3QgZHJtX3BsYW5lIGJhc2U7Cj4gKwlzdHJ1Y3QgbWFsaWRwX2h3X2RldmljZSAq
aHdkZXY7Cj4gKwljb25zdCBzdHJ1Y3QgbWFsaWRwX2xheWVyICpsYXllcjsKPiArCS8qIHNpemUg
b2YgdGhlIHJlcXVpcmVkIHJvdGF0aW9uIG1lbW9yeSB3aGVuIHBsYW5lIGlzIHJvdGF0ZWQgKi8K
PiArCXUzMiByb3RtZW1fc2l6ZTsKPiArfTsKPiArCj4gKyNkZWZpbmUgdG9fbWFsaWRwX3BsYW5l
KHgpIGNvbnRhaW5lcl9vZih4LCBzdHJ1Y3QgbWFsaWRwX3BsYW5lLCBiYXNlKQo+ICsKPiAraW50
IG1hbGlkcF9zZXRfYW5kX3dhaXRfY29uZmlnX3ZhbGlkKHN0cnVjdCBkcm1fZGV2aWNlICpkcm0p
Owo+ICtpbnQgbWFsaWRwX2RlX3BsYW5lc19pbml0KHN0cnVjdCBkcm1fZGV2aWNlICpkcm0pOwo+
ICt2b2lkIG1hbGlkcF9kZV9wbGFuZXNfZGVzdHJveShzdHJ1Y3QgZHJtX2RldmljZSAqZHJtKTsK
PiAraW50IG1hbGlkcF9jcnRjX2luaXQoc3RydWN0IGRybV9kZXZpY2UgKmRybSk7Cj4gKwo+ICsv
KiBvZnRlbiB1c2VkIGNvbWJpbmF0aW9uIG9mIHJvdGF0aW9uYWwgYml0cyAqLwo+ICsjZGVmaW5l
IE1BTElEUF9ST1RBVEVEX01BU0sJKEJJVChEUk1fUk9UQVRFXzkwKSB8IEJJVChEUk1fUk9UQVRF
XzI3MCkpCj4gKwo+ICsjZW5kaWYgIC8qIF9fTUFMSURQX0RSVl9IX18gKi8KPiBkaWZmIC0tZ2l0
IGEvZHJpdmVycy9ncHUvZHJtL2FybS9tYWxpZHBfaHcuYyBiL2RyaXZlcnMvZ3B1L2RybS9hcm0v
bWFsaWRwX2h3LmMKPiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+IGluZGV4IDAwMDAwMDAuLjIyNTE5
ZjQKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2FybS9tYWxpZHBfaHcu
Ywo+IEBAIC0wLDAgKzEsNzc0IEBACj4gKy8qCj4gKyAqIChDKSBDT1BZUklHSFQgMjAxNiBBUk0g
TGltaXRlZC4gQWxsIHJpZ2h0cyByZXNlcnZlZC4KPiArICogQXV0aG9yOiBMaXZpdSBEdWRhdSA8
TGl2aXUuRHVkYXVAYXJtLmNvbT4KPiArICoKPiArICogVGhpcyBwcm9ncmFtIGlzIGZyZWUgc29m
dHdhcmUgYW5kIGlzIHByb3ZpZGVkIHRvIHlvdSB1bmRlciB0aGUgdGVybXMgb2YgdGhlCj4gKyAq
IEdOVSBHZW5lcmFsIFB1YmxpYyBMaWNlbnNlIHZlcnNpb24gMiBhcyBwdWJsaXNoZWQgYnkgdGhl
IEZyZWUgU29mdHdhcmUKPiArICogRm91bmRhdGlvbiwgYW5kIGFueSB1c2UgYnkgeW91IG9mIHRo
aXMgcHJvZ3JhbSBpcyBzdWJqZWN0IHRvIHRoZSB0ZXJtcwo+ICsgKiBvZiBzdWNoIEdOVSBsaWNl
bmNlLgo+ICsgKgo+ICsgKiBBUk0gTWFsaSBEUDUwMC9EUDU1MC9EUDY1MCBoYXJkd2FyZSBtYW5p
cHVsYXRpb24gcm91dGluZXMuIFRoaXMgaXMgd2hlcmUKPiArICogdGhlIGRpZmZlcmVuY2UgYmV0
d2VlbiB2YXJpb3VzIHZlcnNpb25zIG9mIHRoZSBoYXJkd2FyZSBpcyBiZWluZyBkZWFsdCB3aXRo
Cj4gKyAqIGluIGFuIGF0dGVtcHQgdG8gcHJvdmlkZSB0byB0aGUgcmVzdCBvZiB0aGUgZHJpdmVy
IGNvZGUgYSB1bmlmaWVkIHZpZXcKPiArICovCj4gKwo+ICsjaW5jbHVkZSA8bGludXgvdHlwZXMu
aD4KPiArI2luY2x1ZGUgPGxpbnV4L2lvLmg+Cj4gKyNpbmNsdWRlIDxkcm0vZHJtUC5oPgo+ICsj
aW5jbHVkZSA8dmlkZW8vdmlkZW9tb2RlLmg+Cj4gKyNpbmNsdWRlIDx2aWRlby9kaXNwbGF5X3Rp
bWluZy5oPgo+ICsKPiArI2luY2x1ZGUgIm1hbGlkcF9kcnYuaCIKPiArI2luY2x1ZGUgIm1hbGlk
cF9ody5oIgo+ICsjaW5jbHVkZSAibWFsaWRwX3JlZ3MuaCIKPiArCj4gK3N0YXRpYyBjb25zdCBz
dHJ1Y3QgbWFsaWRwX2lucHV0X2Zvcm1hdCBtYWxpZHA1MDBfZGVfZm9ybWF0c1tdID0gewo+ICsJ
LyogICAgbGF5ZXJzIHN1cHBvcnRpbmcgdGhlIGZvcm1hdCwgICAgIGludGVybmFsIGlkLCAgICAg
IGZvdXJjYyAqLwo+ICsJeyBERV9WSURFTzEgfCBERV9HUkFQSElDUzEgfCBERV9HUkFQSElDUzIs
ICAwLCBEUk1fRk9STUFUX0FSR0IyMTAxMDEwIH0sCj4gKwl7IERFX1ZJREVPMSB8IERFX0dSQVBI
SUNTMSB8IERFX0dSQVBISUNTMiwgIDEsIERSTV9GT1JNQVRfQUJHUjIxMDEwMTAgfSwKPiArCXsg
REVfVklERU8xIHwgREVfR1JBUEhJQ1MxIHwgREVfR1JBUEhJQ1MyLCAgMiwgRFJNX0ZPUk1BVF9B
UkdCODg4OCB9LAo+ICsJeyBERV9WSURFTzEgfCBERV9HUkFQSElDUzEgfCBERV9HUkFQSElDUzIs
ICAzLCBEUk1fRk9STUFUX0FCR1I4ODg4IH0sCj4gKwl7IERFX1ZJREVPMSB8IERFX0dSQVBISUNT
MSB8IERFX0dSQVBISUNTMiwgIDQsIERSTV9GT1JNQVRfWFJHQjg4ODggfSwKPiArCXsgREVfVklE
RU8xIHwgREVfR1JBUEhJQ1MxIHwgREVfR1JBUEhJQ1MyLCAgNSwgRFJNX0ZPUk1BVF9YQkdSODg4
OCB9LAo+ICsJeyBERV9WSURFTzEgfCBERV9HUkFQSElDUzEgfCBERV9HUkFQSElDUzIsICA2LCBE
Uk1fRk9STUFUX1JHQjg4OCB9LAo+ICsJeyBERV9WSURFTzEgfCBERV9HUkFQSElDUzEgfCBERV9H
UkFQSElDUzIsICA3LCBEUk1fRk9STUFUX0JHUjg4OCB9LAo+ICsJeyBERV9WSURFTzEgfCBERV9H
UkFQSElDUzEgfCBERV9HUkFQSElDUzIsICA4LCBEUk1fRk9STUFUX1JHQkE1NTUxIH0sCj4gKwl7
IERFX1ZJREVPMSB8IERFX0dSQVBISUNTMSB8IERFX0dSQVBISUNTMiwgIDksIERSTV9GT1JNQVRf
QUJHUjE1NTUgfSwKPiArCXsgREVfVklERU8xIHwgREVfR1JBUEhJQ1MxIHwgREVfR1JBUEhJQ1My
LCAxMCwgRFJNX0ZPUk1BVF9SR0I1NjUgfSwKPiArCXsgREVfVklERU8xIHwgREVfR1JBUEhJQ1Mx
IHwgREVfR1JBUEhJQ1MyLCAxMSwgRFJNX0ZPUk1BVF9CR1I1NjUgfSwKPiArCXsgREVfVklERU8x
LCAxMiwgRFJNX0ZPUk1BVF9VWVZZIH0sCj4gKwl7IERFX1ZJREVPMSwgMTMsIERSTV9GT1JNQVRf
WVVZViB9LAo+ICsJeyBERV9WSURFTzEsIDE0LCBEUk1fRk9STUFUX05WMTIgfSwKPiArCXsgREVf
VklERU8xLCAxNSwgRFJNX0ZPUk1BVF9ZVVY0MjAgfSwKPiArfTsKPiArCj4gKyNkZWZpbmUgTUFM
SURQX0lEKF9fZ3JvdXAsIF9fZm9ybWF0KSBcCj4gKwkoKCgoX19ncm91cCkgJiAweDcpIDw8IDMp
IHwgKChfX2Zvcm1hdCkgJiAweDcpKQo+ICsKPiArI2RlZmluZSBNQUxJRFBfQ09NTU9OX0ZPUk1B
VFMgXAo+ICsJLyogICAgbGF5ZXJzIHN1cHBvcnRpbmcgdGhlIGZvcm1hdCwgICAgICBpbnRlcm5h
bCBpZCwgICAgICBmb3VyY2MgKi8gXAo+ICsJeyBERV9WSURFTzEgfCBERV9HUkFQSElDUzEgfCBE
RV9WSURFTzIsIE1BTElEUF9JRCgwLCAwKSwgRFJNX0ZPUk1BVF9BUkdCMjEwMTAxMCB9LCBcCj4g
Kwl7IERFX1ZJREVPMSB8IERFX0dSQVBISUNTMSB8IERFX1ZJREVPMiwgTUFMSURQX0lEKDAsIDEp
LCBEUk1fRk9STUFUX0FCR1IyMTAxMDEwIH0sIFwKPiArCXsgREVfVklERU8xIHwgREVfR1JBUEhJ
Q1MxIHwgREVfVklERU8yLCBNQUxJRFBfSUQoMCwgMiksIERSTV9GT1JNQVRfUkdCQTEwMTAxMDIg
fSwgXAo+ICsJeyBERV9WSURFTzEgfCBERV9HUkFQSElDUzEgfCBERV9WSURFTzIsIE1BTElEUF9J
RCgwLCAzKSwgRFJNX0ZPUk1BVF9CR1JBMTAxMDEwMiB9LCBcCj4gKwl7IERFX1ZJREVPMSB8IERF
X0dSQVBISUNTMSB8IERFX1ZJREVPMiB8IERFX1NNQVJULCBNQUxJRFBfSUQoMSwgMCksIERSTV9G
T1JNQVRfQVJHQjg4ODggfSwgXAo+ICsJeyBERV9WSURFTzEgfCBERV9HUkFQSElDUzEgfCBERV9W
SURFTzIgfCBERV9TTUFSVCwgTUFMSURQX0lEKDEsIDEpLCBEUk1fRk9STUFUX0FCR1I4ODg4IH0s
IFwKPiArCXsgREVfVklERU8xIHwgREVfR1JBUEhJQ1MxIHwgREVfVklERU8yIHwgREVfU01BUlQs
IE1BTElEUF9JRCgxLCAyKSwgRFJNX0ZPUk1BVF9SR0JBODg4OCB9LCBcCj4gKwl7IERFX1ZJREVP
MSB8IERFX0dSQVBISUNTMSB8IERFX1ZJREVPMiB8IERFX1NNQVJULCBNQUxJRFBfSUQoMSwgMyks
IERSTV9GT1JNQVRfQkdSQTg4ODggfSwgXAo+ICsJeyBERV9WSURFTzEgfCBERV9HUkFQSElDUzEg
fCBERV9WSURFTzIgfCBERV9TTUFSVCwgTUFMSURQX0lEKDIsIDApLCBEUk1fRk9STUFUX1hSR0I4
ODg4IH0sIFwKPiArCXsgREVfVklERU8xIHwgREVfR1JBUEhJQ1MxIHwgREVfVklERU8yIHwgREVf
U01BUlQsIE1BTElEUF9JRCgyLCAxKSwgRFJNX0ZPUk1BVF9YQkdSODg4OCB9LCBcCj4gKwl7IERF
X1ZJREVPMSB8IERFX0dSQVBISUNTMSB8IERFX1ZJREVPMiB8IERFX1NNQVJULCBNQUxJRFBfSUQo
MiwgMiksIERSTV9GT1JNQVRfUkdCWDg4ODggfSwgXAo+ICsJeyBERV9WSURFTzEgfCBERV9HUkFQ
SElDUzEgfCBERV9WSURFTzIgfCBERV9TTUFSVCwgTUFMSURQX0lEKDIsIDMpLCBEUk1fRk9STUFU
X0JHUlg4ODg4IH0sIFwKPiArCXsgREVfVklERU8xIHwgREVfR1JBUEhJQ1MxIHwgREVfVklERU8y
LCBNQUxJRFBfSUQoMywgMCksIERSTV9GT1JNQVRfUkdCODg4IH0sIFwKPiArCXsgREVfVklERU8x
IHwgREVfR1JBUEhJQ1MxIHwgREVfVklERU8yLCBNQUxJRFBfSUQoMywgMSksIERSTV9GT1JNQVRf
QkdSODg4IH0sIFwKPiArCXsgREVfVklERU8xIHwgREVfR1JBUEhJQ1MxIHwgREVfVklERU8yLCBN
QUxJRFBfSUQoNCwgMCksIERSTV9GT1JNQVRfUkdCQTU1NTEgfSwgXAo+ICsJeyBERV9WSURFTzEg
fCBERV9HUkFQSElDUzEgfCBERV9WSURFTzIsIE1BTElEUF9JRCg0LCAxKSwgRFJNX0ZPUk1BVF9B
QkdSMTU1NSB9LCBcCj4gKwl7IERFX1ZJREVPMSB8IERFX0dSQVBISUNTMSB8IERFX1ZJREVPMiwg
TUFMSURQX0lEKDQsIDIpLCBEUk1fRk9STUFUX1JHQjU2NSB9LAlcCj4gKwl7IERFX1ZJREVPMSB8
IERFX0dSQVBISUNTMSB8IERFX1ZJREVPMiwgTUFMSURQX0lEKDQsIDMpLCBEUk1fRk9STUFUX0JH
UjU2NSB9LAlcCj4gKwl7IERFX1ZJREVPMSB8IERFX1ZJREVPMiwgTUFMSURQX0lEKDUsIDIpLCBE
Uk1fRk9STUFUX1lVWVYgfSwgXAo+ICsJeyBERV9WSURFTzEgfCBERV9WSURFTzIsIE1BTElEUF9J
RCg1LCAzKSwgRFJNX0ZPUk1BVF9VWVZZIH0sIFwKPiArCXsgREVfVklERU8xIHwgREVfVklERU8y
LCBNQUxJRFBfSUQoNSwgNiksIERSTV9GT1JNQVRfTlYxMiB9LCBcCj4gKwl7IERFX1ZJREVPMSB8
IERFX1ZJREVPMiwgTUFMSURQX0lEKDUsIDcpLCBEUk1fRk9STUFUX1lVVjQyMCB9Cj4gKwo+ICtz
dGF0aWMgY29uc3Qgc3RydWN0IG1hbGlkcF9pbnB1dF9mb3JtYXQgbWFsaWRwNTUwX2RlX2Zvcm1h
dHNbXSA9IHsKPiArCU1BTElEUF9DT01NT05fRk9STUFUUywKPiArfTsKPiArCj4gK3N0YXRpYyBj
b25zdCBzdHJ1Y3QgbWFsaWRwX2lucHV0X2Zvcm1hdCBtYWxpZHA2NTBfZGVfZm9ybWF0c1tdID0g
ewo+ICsJTUFMSURQX0NPTU1PTl9GT1JNQVRTLAo+ICt9Owo+ICsKPiArc3RhdGljIGNvbnN0IHN0
cnVjdCBtYWxpZHBfbGF5ZXIgbWFsaWRwNTAwX2xheWVyc1tdID0gewo+ICsJeyBERV9WSURFTzEs
IE1BTElEUDUwMF9ERV9MVl9CQVNFLCBNQUxJRFA1MDBfREVfTFZfUFRSX0JBU0UgfSwKPiArCXsg
REVfR1JBUEhJQ1MxLCBNQUxJRFA1MDBfREVfTEcxX0JBU0UsIE1BTElEUDUwMF9ERV9MRzFfUFRS
X0JBU0UgfSwKPiArCXsgREVfR1JBUEhJQ1MyLCBNQUxJRFA1MDBfREVfTEcyX0JBU0UsIE1BTElE
UDUwMF9ERV9MRzJfUFRSX0JBU0UgfSwKPiArfTsKPiArCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qg
bWFsaWRwX2xheWVyIG1hbGlkcDU1MF9sYXllcnNbXSA9IHsKPiArCXsgREVfVklERU8xLCBNQUxJ
RFA1NTBfREVfTFYxX0JBU0UsIE1BTElEUDU1MF9ERV9MVjFfUFRSX0JBU0UgfSwKPiArCXsgREVf
R1JBUEhJQ1MxLCBNQUxJRFA1NTBfREVfTEdfQkFTRSwgTUFMSURQNTUwX0RFX0xHX1BUUl9CQVNF
IH0sCj4gKwl7IERFX1ZJREVPMiwgTUFMSURQNTUwX0RFX0xWMl9CQVNFLCBNQUxJRFA1NTBfREVf
TFYyX1BUUl9CQVNFIH0sCj4gKwl7IERFX1NNQVJULCBNQUxJRFA1NTBfREVfTFNfQkFTRSwgTUFM
SURQNTUwX0RFX0xTX1BUUl9CQVNFIH0sCj4gK307Cj4gKwo+ICsjZGVmaW5lIE1BTElEUF9ERV9E
RUZBVUxUX1BSRUZFVENIX1NUQVJUCTUKPiArCj4gK2ludCBtYWxpZHA1MDBfcXVlcnlfaHcoc3Ry
dWN0IG1hbGlkcF9od19kZXZpY2UgKmh3ZGV2KQo+ICt7Cj4gKwl1MzIgY29uZiA9IG1hbGlkcF9o
d19yZWFkKGh3ZGV2LCBNQUxJRFA1MDBfQ09ORklHX0lEKTsKPiArCS8qIGJpdCA0IG9mIHRoZSBD
T05GSUdfSUQgcmVnaXN0ZXIgaG9sZHMgdGhlIGxpbmUgc2l6ZSBtdWx0aXBsaWVyICovCj4gKwl1
OCBsbl9zaXplX211bHQgPSBjb25mICYgMHgxMCA/IDIgOiAxOwo+ICsKPiArCWh3ZGV2LT5taW5f
bGluZV9zaXplID0gMjsKPiArCWh3ZGV2LT5tYXhfbGluZV9zaXplID0gU1pfMksgKiBsbl9zaXpl
X211bHQ7Cj4gKwlod2Rldi0+cm90YXRpb25fbWVtb3J5WzBdID0gU1pfMUsgKiA2NCAqIGxuX3Np
emVfbXVsdDsKPiArCWh3ZGV2LT5yb3RhdGlvbl9tZW1vcnlbMV0gPSAwOyAvKiBubyBzZWNvbmQg
cm90YXRpb24gbWVtb3J5IGJhbmsgKi8KPiArCj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiArdm9p
ZCBtYWxpZHA1MDBfZW50ZXJfY29uZmlnX21vZGUoc3RydWN0IG1hbGlkcF9od19kZXZpY2UgKmh3
ZGV2KQo+ICt7Cj4gKwl1MzIgc3RhdHVzLCBjb3VudCA9IDEwMDsKPiArCj4gKwltYWxpZHBfaHdf
c2V0Yml0cyhod2RldiwgTUFMSURQNTAwX0RDX0NPTkZJR19SRVEsIE1BTElEUDUwMF9EQ19DT05U
Uk9MKTsKPiArCXdoaWxlIChjb3VudCkgewo+ICsJCXN0YXR1cyA9IG1hbGlkcF9od19yZWFkKGh3
ZGV2LCBod2Rldi0+bWFwLmRjX2Jhc2UgKyBNQUxJRFBfUkVHX1NUQVRVUyk7Cj4gKwkJaWYgKChz
dGF0dXMgJiBNQUxJRFA1MDBfRENfQ09ORklHX1JFUSkgPT0gTUFMSURQNTAwX0RDX0NPTkZJR19S
RVEpCj4gKwkJCWJyZWFrOwo+ICsJCS8qCj4gKwkJICogZW50ZXJpbmcgY29uZmlnIG1vZGUgY2Fu
IHRha2UgYXMgbG9uZyBhcyB0aGUgcmVuZGVyaW5nCj4gKwkJICogb2YgYSBmdWxsIGZyYW1lLCBo
ZW5jZSB0aGUgbG9uZyBzbGVlcCBoZXJlCj4gKwkJICovCj4gKwkJdXNsZWVwX3JhbmdlKDEwMDAs
IDEwMDAwKTsKPiArCQljb3VudC0tOwo+ICsJfQo+ICsJV0FSTihjb3VudCA9PSAwLCAidGltZW91
dCB3aGlsZSBlbnRlcmluZyBjb25maWcgbW9kZSIpOwo+ICt9Cj4gKwo+ICt2b2lkIG1hbGlkcDUw
MF9sZWF2ZV9jb25maWdfbW9kZShzdHJ1Y3QgbWFsaWRwX2h3X2RldmljZSAqaHdkZXYpCj4gK3sK
PiArCXUzMiBzdGF0dXMsIGNvdW50ID0gMzA7Cj4gKwo+ICsJbWFsaWRwX2h3X2NsZWFyYml0cyho
d2RldiwgTUFMSURQNTAwX0RDX0NPTkZJR19SRVEsIE1BTElEUDUwMF9EQ19DT05UUk9MKTsKPiAr
CXdoaWxlIChjb3VudCkgewo+ICsJCXN0YXR1cyA9IG1hbGlkcF9od19yZWFkKGh3ZGV2LCBod2Rl
di0+bWFwLmRjX2Jhc2UgKyBNQUxJRFBfUkVHX1NUQVRVUyk7Cj4gKwkJaWYgKChzdGF0dXMgJiBN
QUxJRFA1MDBfRENfQ09ORklHX1JFUSkgPT0gMCkKPiArCQkJYnJlYWs7Cj4gKwkJdXNsZWVwX3Jh
bmdlKDEwMCwgMTAwMCk7Cj4gKwkJY291bnQtLTsKPiArCX0KPiArCVdBUk4oY291bnQgPT0gMCwg
InRpbWVvdXQgd2hpbGUgbGVhdmluZyBjb25maWcgbW9kZSIpOwo+ICt9Cj4gKwo+ICtib29sIG1h
bGlkcDUwMF9pbl9jb25maWdfbW9kZShzdHJ1Y3QgbWFsaWRwX2h3X2RldmljZSAqaHdkZXYpCj4g
K3sKPiArCXUzMiBzdGF0dXM7Cj4gKwo+ICsJc3RhdHVzID0gbWFsaWRwX2h3X3JlYWQoaHdkZXYs
IGh3ZGV2LT5tYXAuZGNfYmFzZSArIE1BTElEUF9SRUdfU1RBVFVTKTsKPiArCWlmICgoc3RhdHVz
ICYgTUFMSURQNTAwX0RDX0NPTkZJR19SRVEpID09IE1BTElEUDUwMF9EQ19DT05GSUdfUkVRKQo+
ICsJCXJldHVybiB0cnVlOwo+ICsKPiArCXJldHVybiBmYWxzZTsKPiArfQo+ICsKPiArdm9pZCBt
YWxpZHA1MDBfc2V0X2NvbmZpZ192YWxpZChzdHJ1Y3QgbWFsaWRwX2h3X2RldmljZSAqaHdkZXYp
Cj4gK3sKPiArCW1hbGlkcF9od19zZXRiaXRzKGh3ZGV2LCBNQUxJRFBfQ0ZHX1ZBTElELCBNQUxJ
RFA1MDBfQ09ORklHX1ZBTElEKTsKPiArfQo+ICsKPiArdm9pZCBtYWxpZHA1MDBfbW9kZXNldChz
dHJ1Y3QgbWFsaWRwX2h3X2RldmljZSAqaHdkZXYsIHN0cnVjdCB2aWRlb21vZGUgKm1vZGUpCj4g
K3sKPiArCXUzMiB2YWwgPSAwOwo+ICsKPiArCW1hbGlkcF9od19jbGVhcmJpdHMoaHdkZXYsIE1B
TElEUDUwMF9EQ19DTEVBUl9NQVNLLCBNQUxJRFA1MDBfRENfQ09OVFJPTCk7Cj4gKwlpZiAobW9k
ZS0+ZmxhZ3MgJiBESVNQTEFZX0ZMQUdTX0hTWU5DX0hJR0gpCj4gKwkJdmFsIHw9IE1BTElEUDUw
MF9IU1lOQ1BPTDsKPiArCWlmIChtb2RlLT5mbGFncyAmIERJU1BMQVlfRkxBR1NfVlNZTkNfSElH
SCkKPiArCQl2YWwgfD0gTUFMSURQNTAwX1ZTWU5DUE9MOwo+ICsJdmFsIHw9IE1BTElEUF9ERV9E
RUZBVUxUX1BSRUZFVENIX1NUQVJUOwo+ICsJbWFsaWRwX2h3X3NldGJpdHMoaHdkZXYsIHZhbCwg
TUFMSURQNTAwX0RDX0NPTlRST0wpOwo+ICsKPiArCS8qCj4gKwkgKiBNYWxpLURQNTAwIGVuY29k
ZXMgdGhlIGJhY2tncm91bmQgY29sb3IgbGlrZSB0aGlzOgo+ICsJICogICAgLSByZWQgICBAIE1B
TElEUDUwMF9CR05EX0NPTE9SWzEyOjBdCj4gKwkgKiAgICAtIGdyZWVuIEAgTUFMSURQNTAwX0JH
TkRfQ09MT1JbMjc6MTZdCj4gKwkgKiAgICAtIGJsdWUgIEAgKE1BTElEUDUwMF9CR05EX0NPTE9S
ICsgNClbMTI6MF0KPiArCSAqLwo+ICsJdmFsID0gKChNQUxJRFBfQkdORF9DT0xPUl9HICYgMHhm
ZmYpIDw8IDE2KSB8Cj4gKwkgICAgICAoTUFMSURQX0JHTkRfQ09MT1JfUiAmIDB4ZmZmKTsKPiAr
CW1hbGlkcF9od193cml0ZShod2RldiwgdmFsLCBNQUxJRFA1MDBfQkdORF9DT0xPUik7Cj4gKwlt
YWxpZHBfaHdfd3JpdGUoaHdkZXYsIE1BTElEUF9CR05EX0NPTE9SX0IsIE1BTElEUDUwMF9CR05E
X0NPTE9SICsgNCk7Cj4gKwo+ICsJdmFsID0gTUFMSURQX0RFX0hfRlJPTlRQT1JDSChtb2RlLT5o
ZnJvbnRfcG9yY2gpIHwKPiArCQlNQUxJRFBfREVfSF9CQUNLUE9SQ0gobW9kZS0+aGJhY2tfcG9y
Y2gpOwo+ICsJbWFsaWRwX2h3X3dyaXRlKGh3ZGV2LCB2YWwsIE1BTElEUDUwMF9USU1JTkdTX0JB
U0UgKyBNQUxJRFBfREVfSF9USU1JTkdTKTsKPiArCj4gKwl2YWwgPSBNQUxJRFA1MDBfREVfVl9G
Uk9OVFBPUkNIKG1vZGUtPnZmcm9udF9wb3JjaCkgfAo+ICsJCU1BTElEUF9ERV9WX0JBQ0tQT1JD
SChtb2RlLT52YmFja19wb3JjaCk7Cj4gKwltYWxpZHBfaHdfd3JpdGUoaHdkZXYsIHZhbCwgTUFM
SURQNTAwX1RJTUlOR1NfQkFTRSArIE1BTElEUF9ERV9WX1RJTUlOR1MpOwo+ICsKPiArCXZhbCA9
IE1BTElEUF9ERV9IX1NZTkNXSURUSChtb2RlLT5oc3luY19sZW4pIHwKPiArCQlNQUxJRFBfREVf
Vl9TWU5DV0lEVEgobW9kZS0+dnN5bmNfbGVuKTsKPiArCW1hbGlkcF9od193cml0ZShod2Rldiwg
dmFsLCBNQUxJRFA1MDBfVElNSU5HU19CQVNFICsgTUFMSURQX0RFX1NZTkNfV0lEVEgpOwo+ICsK
PiArCXZhbCA9IE1BTElEUF9ERV9IX0FDVElWRShtb2RlLT5oYWN0aXZlKSB8IE1BTElEUF9ERV9W
X0FDVElWRShtb2RlLT52YWN0aXZlKTsKPiArCW1hbGlkcF9od193cml0ZShod2RldiwgdmFsLCBN
QUxJRFA1MDBfVElNSU5HU19CQVNFICsgTUFMSURQX0RFX0hWX0FDVElWRSk7Cj4gKwo+ICsJaWYg
KG1vZGUtPmZsYWdzICYgRElTUExBWV9GTEFHU19JTlRFUkxBQ0VEKQo+ICsJCW1hbGlkcF9od19z
ZXRiaXRzKGh3ZGV2LCBNQUxJRFBfRElTUF9GVU5DX0lMQUNFRCwgTUFMSURQX0RFX0RJU1BMQVlf
RlVOQyk7Cj4gKwllbHNlCj4gKwkJbWFsaWRwX2h3X2NsZWFyYml0cyhod2RldiwgTUFMSURQX0RJ
U1BfRlVOQ19JTEFDRUQsIE1BTElEUF9ERV9ESVNQTEFZX0ZVTkMpOwo+ICt9Cj4gKwo+ICtpbnQg
bWFsaWRwNTAwX3JvdG1lbV9yZXF1aXJlZChzdHJ1Y3QgbWFsaWRwX2h3X2RldmljZSAqaHdkZXYs
IHUxNiB3LCB1MTYgaCwgdTMyIGZtdCkKPiArewo+ICsJdW5zaWduZWQgaW50IGRlcHRoOwo+ICsJ
aW50IGJwcDsKPiArCj4gKwkvKiBSR0I4ODggb3IgQkdSODg4IGNhbid0IGJlIHJvdGF0ZWQgKi8K
PiArCWlmICgoZm10ID09IERSTV9GT1JNQVRfUkdCODg4KSB8fCAoZm10ID09IERSTV9GT1JNQVRf
QkdSODg4KSkKPiArCQlyZXR1cm4gLUVJTlZBTDsKPiArCj4gKwkvKgo+ICsJICogRWFjaCBsYXll
ciBuZWVkcyBlbm91Z2ggcm90YXRpb24gbWVtb3J5IHRvIGZpdCA4IGxpbmVzCj4gKwkgKiB3b3J0
aCBvZiBwaXhlbCBkYXRhLiBSZXF1aXJlZCBzaXplIGlzIHRoZW46Cj4gKwkgKiAgICBzaXplID0g
KHJvdGF0ZWRfd2lkdGggKiBicHAgKiA4ICkgLyA4Owo+ICsJICovCj4gKwlkcm1fZmJfZ2V0X2Jw
cF9kZXB0aChmbXQsICZkZXB0aCwgJmJwcCk7Cj4gKwo+ICsJcmV0dXJuIHcgKiBicHA7Cj4gK30K
PiArCj4gK3N0YXRpYyBpbnQgbWFsaWRwNTUwX3F1ZXJ5X2h3KHN0cnVjdCBtYWxpZHBfaHdfZGV2
aWNlICpod2RldikKPiArewo+ICsJdTMyIGNvbmYgPSBtYWxpZHBfaHdfcmVhZChod2RldiwgTUFM
SURQNTUwX0NPTkZJR19JRCk7Cj4gKwl1OCBsbl9zaXplID0gKGNvbmYgPj4gNCkgJiAweDMsIHJz
aXplOwo+ICsKPiArCWh3ZGV2LT5taW5fbGluZV9zaXplID0gMjsKPiArCj4gKwlzd2l0Y2ggKGxu
X3NpemUpIHsKPiArCWNhc2UgMDoKPiArCQlod2Rldi0+bWF4X2xpbmVfc2l6ZSA9IFNaXzJLOwo+
ICsJCS8qIHR3byBiYW5rcyBvZiA2NEtCIGZvciByb3RhdGlvbiBtZW1vcnkgKi8KPiArCQlyc2l6
ZSA9IDY0Owo+ICsJCWJyZWFrOwo+ICsJY2FzZSAxOgo+ICsJCWh3ZGV2LT5tYXhfbGluZV9zaXpl
ID0gU1pfNEs7Cj4gKwkJLyogdHdvIGJhbmtzIG9mIDEyOEtCIGZvciByb3RhdGlvbiBtZW1vcnkg
Ki8KPiArCQlyc2l6ZSA9IDEyODsKPiArCQlicmVhazsKPiArCWNhc2UgMjoKPiArCQlod2Rldi0+
bWF4X2xpbmVfc2l6ZSA9IDEyODA7Cj4gKwkJLyogdHdvIGJhbmtzIG9mIDQwS0IgZm9yIHJvdGF0
aW9uIG1lbW9yeSAqLwo+ICsJCXJzaXplID0gNDA7Cj4gKwkJYnJlYWs7Cj4gKwljYXNlIDM6Cj4g
KwkJLyogcmVzZXJ2ZWQgdmFsdWUgKi8KPiArCQlod2Rldi0+bWF4X2xpbmVfc2l6ZSA9IDA7Cj4g
KwkJcmV0dXJuIC1FSU5WQUw7Cj4gKwl9Cj4gKwo+ICsJaHdkZXYtPnJvdGF0aW9uX21lbW9yeVsw
XSA9IGh3ZGV2LT5yb3RhdGlvbl9tZW1vcnlbMV0gPSByc2l6ZSAqIFNaXzFLOwo+ICsJcmV0dXJu
IDA7Cj4gK30KPiArCj4gK3ZvaWQgbWFsaWRwNTUwX2VudGVyX2NvbmZpZ19tb2RlKHN0cnVjdCBt
YWxpZHBfaHdfZGV2aWNlICpod2RldikKPiArewo+ICsJdTMyIHN0YXR1cywgY291bnQgPSAxMDA7
Cj4gKwo+ICsJbWFsaWRwX2h3X3NldGJpdHMoaHdkZXYsIE1BTElEUDU1MF9EQ19DT05GSUdfUkVR
LCBNQUxJRFA1NTBfRENfQ09OVFJPTCk7Cj4gKwl3aGlsZSAoY291bnQpIHsKPiArCQlzdGF0dXMg
PSBtYWxpZHBfaHdfcmVhZChod2RldiwgaHdkZXYtPm1hcC5kY19iYXNlICsgTUFMSURQX1JFR19T
VEFUVVMpOwo+ICsJCWlmICgoc3RhdHVzICYgTUFMSURQNTUwX0RDX0NPTkZJR19SRVEpID09IE1B
TElEUDU1MF9EQ19DT05GSUdfUkVRKQo+ICsJCQlicmVhazsKPiArCQkvKgo+ICsJCSAqIGVudGVy
aW5nIGNvbmZpZyBtb2RlIGNhbiB0YWtlIGFzIGxvbmcgYXMgdGhlIHJlbmRlcmluZwo+ICsJCSAq
IG9mIGEgZnVsbCBmcmFtZSwgaGVuY2UgdGhlIGxvbmcgc2xlZXAgaGVyZQo+ICsJCSAqLwo+ICsJ
CXVzbGVlcF9yYW5nZSgxMDAwLCAxMDAwMCk7Cj4gKwkJY291bnQtLTsKPiArCX0KPiArCVdBUk4o
Y291bnQgPT0gMCwgInRpbWVvdXQgd2hpbGUgZW50ZXJpbmcgY29uZmlnIG1vZGUiKTsKPiArfQo+
ICsKPiArdm9pZCBtYWxpZHA1NTBfbGVhdmVfY29uZmlnX21vZGUoc3RydWN0IG1hbGlkcF9od19k
ZXZpY2UgKmh3ZGV2KQo+ICt7Cj4gKwl1MzIgc3RhdHVzLCBjb3VudCA9IDMwOwo+ICsKPiArCW1h
bGlkcF9od19jbGVhcmJpdHMoaHdkZXYsIE1BTElEUDU1MF9EQ19DT05GSUdfUkVRLCBNQUxJRFA1
NTBfRENfQ09OVFJPTCk7Cj4gKwl3aGlsZSAoY291bnQpIHsKPiArCQlzdGF0dXMgPSBtYWxpZHBf
aHdfcmVhZChod2RldiwgaHdkZXYtPm1hcC5kY19iYXNlICsgTUFMSURQX1JFR19TVEFUVVMpOwo+
ICsJCWlmICgoc3RhdHVzICYgTUFMSURQNTUwX0RDX0NPTkZJR19SRVEpID09IDApCj4gKwkJCWJy
ZWFrOwo+ICsJCXVzbGVlcF9yYW5nZSgxMDAsIDEwMDApOwo+ICsJCWNvdW50LS07Cj4gKwl9Cj4g
KwlXQVJOKGNvdW50ID09IDAsICJ0aW1lb3V0IHdoaWxlIGxlYXZpbmcgY29uZmlnIG1vZGUiKTsK
PiArfQo+ICsKPiArYm9vbCBtYWxpZHA1NTBfaW5fY29uZmlnX21vZGUoc3RydWN0IG1hbGlkcF9o
d19kZXZpY2UgKmh3ZGV2KQo+ICt7Cj4gKwl1MzIgc3RhdHVzOwo+ICsKPiArCXN0YXR1cyA9IG1h
bGlkcF9od19yZWFkKGh3ZGV2LCBod2Rldi0+bWFwLmRjX2Jhc2UgKyBNQUxJRFBfUkVHX1NUQVRV
Uyk7Cj4gKwlpZiAoKHN0YXR1cyAmIE1BTElEUDU1MF9EQ19DT05GSUdfUkVRKSA9PSBNQUxJRFA1
NTBfRENfQ09ORklHX1JFUSkKPiArCQlyZXR1cm4gdHJ1ZTsKPiArCj4gKwlyZXR1cm4gZmFsc2U7
Cj4gK30KPiArCj4gK3ZvaWQgbWFsaWRwNTUwX3NldF9jb25maWdfdmFsaWQoc3RydWN0IG1hbGlk
cF9od19kZXZpY2UgKmh3ZGV2KQo+ICt7Cj4gKwltYWxpZHBfaHdfc2V0Yml0cyhod2RldiwgTUFM
SURQX0NGR19WQUxJRCwgTUFMSURQNTUwX0NPTkZJR19WQUxJRCk7Cj4gK30KPiArCj4gK3ZvaWQg
bWFsaWRwNTUwX21vZGVzZXQoc3RydWN0IG1hbGlkcF9od19kZXZpY2UgKmh3ZGV2LCBzdHJ1Y3Qg
dmlkZW9tb2RlICptb2RlKQo+ICt7Cj4gKwl1MzIgdmFsID0gTUFMSURQX0RFX0RFRkFVTFRfUFJF
RkVUQ0hfU1RBUlQ7Cj4gKwo+ICsJbWFsaWRwX2h3X3dyaXRlKGh3ZGV2LCB2YWwsIE1BTElEUDU1
MF9ERV9DT05UUk9MKTsKPiArCS8qCj4gKwkgKiBNYWxpLURQNTUwIGFuZCBNYWxpLURQNjUwIGVu
Y29kZSB0aGUgYmFja2dyb3VuZCBjb2xvciBsaWtlIHRoaXM6Cj4gKwkgKiAgIC0gcmVkICAgQCBN
QUxJRFA1NTBfREVfQkdORF9DT0xPUlsyMzoxNl0KPiArCSAqICAgLSBncmVlbiBAIE1BTElEUDU1
MF9ERV9CR05EX0NPTE9SWzE1OjhdCj4gKwkgKiAgIC0gYmx1ZSAgQCBNQUxJRFA1NTBfREVfQkdO
RF9DT0xPUls3OjBdCj4gKwkgKgo+ICsJICogV2UgbmVlZCB0byB0cnVuY2F0ZSB0aGUgbGVhc3Qg
c2lnbmlmaWNhbnQgNCBiaXRzIGZyb20gdGhlIGRlZmF1bHQKPiArCSAqIE1BTElEUF9CR05EX0NP
TE9SX3ggdmFsdWVzCj4gKwkgKi8KPiArCXZhbCA9ICgoKE1BTElEUF9CR05EX0NPTE9SX1IgPj4g
NCkgJiAweGZmKSA8PCAxNikgfAo+ICsJICAgICAgKCgoTUFMSURQX0JHTkRfQ09MT1JfRyA+PiA0
KSAmIDB4ZmYpIDw8IDgpIHwKPiArCSAgICAgICgoTUFMSURQX0JHTkRfQ09MT1JfQiA+PiA0KSAm
IDB4ZmYpOwo+ICsJbWFsaWRwX2h3X3dyaXRlKGh3ZGV2LCB2YWwsIE1BTElEUDU1MF9ERV9CR05E
X0NPTE9SKTsKPiArCj4gKwl2YWwgPSBNQUxJRFBfREVfSF9GUk9OVFBPUkNIKG1vZGUtPmhmcm9u
dF9wb3JjaCkgfAo+ICsJCU1BTElEUF9ERV9IX0JBQ0tQT1JDSChtb2RlLT5oYmFja19wb3JjaCk7
Cj4gKwltYWxpZHBfaHdfd3JpdGUoaHdkZXYsIHZhbCwgTUFMSURQNTUwX1RJTUlOR1NfQkFTRSAr
IE1BTElEUF9ERV9IX1RJTUlOR1MpOwo+ICsKPiArCXZhbCA9IE1BTElEUDU1MF9ERV9WX0ZST05U
UE9SQ0gobW9kZS0+dmZyb250X3BvcmNoKSB8Cj4gKwkJTUFMSURQX0RFX1ZfQkFDS1BPUkNIKG1v
ZGUtPnZiYWNrX3BvcmNoKTsKPiArCW1hbGlkcF9od193cml0ZShod2RldiwgdmFsLCBNQUxJRFA1
NTBfVElNSU5HU19CQVNFICsgTUFMSURQX0RFX1ZfVElNSU5HUyk7Cj4gKwo+ICsJdmFsID0gTUFM
SURQX0RFX0hfU1lOQ1dJRFRIKG1vZGUtPmhzeW5jX2xlbikgfAo+ICsJCU1BTElEUF9ERV9WX1NZ
TkNXSURUSChtb2RlLT52c3luY19sZW4pOwo+ICsJaWYgKG1vZGUtPmZsYWdzICYgRElTUExBWV9G
TEFHU19IU1lOQ19ISUdIKQo+ICsJCXZhbCB8PSBNQUxJRFA1NTBfSFNZTkNQT0w7Cj4gKwlpZiAo
bW9kZS0+ZmxhZ3MgJiBESVNQTEFZX0ZMQUdTX1ZTWU5DX0hJR0gpCj4gKwkJdmFsIHw9IE1BTElE
UDU1MF9WU1lOQ1BPTDsKPiArCW1hbGlkcF9od193cml0ZShod2RldiwgdmFsLCBNQUxJRFA1NTBf
VElNSU5HU19CQVNFICsgTUFMSURQX0RFX1NZTkNfV0lEVEgpOwo+ICsKPiArCXZhbCA9IE1BTElE
UF9ERV9IX0FDVElWRShtb2RlLT5oYWN0aXZlKSB8IE1BTElEUF9ERV9WX0FDVElWRShtb2RlLT52
YWN0aXZlKTsKPiArCW1hbGlkcF9od193cml0ZShod2RldiwgdmFsLCBNQUxJRFA1NTBfVElNSU5H
U19CQVNFICsgTUFMSURQX0RFX0hWX0FDVElWRSk7Cj4gKwo+ICsJaWYgKG1vZGUtPmZsYWdzICYg
RElTUExBWV9GTEFHU19JTlRFUkxBQ0VEKQo+ICsJCW1hbGlkcF9od19zZXRiaXRzKGh3ZGV2LCBN
QUxJRFBfRElTUF9GVU5DX0lMQUNFRCwgTUFMSURQX0RFX0RJU1BMQVlfRlVOQyk7Cj4gKwllbHNl
Cj4gKwkJbWFsaWRwX2h3X2NsZWFyYml0cyhod2RldiwgTUFMSURQX0RJU1BfRlVOQ19JTEFDRUQs
IE1BTElEUF9ERV9ESVNQTEFZX0ZVTkMpOwo+ICt9Cj4gKwo+ICtpbnQgbWFsaWRwNTUwX3JvdG1l
bV9yZXF1aXJlZChzdHJ1Y3QgbWFsaWRwX2h3X2RldmljZSAqaHdkZXYsIHUxNiB3LCB1MTYgaCwg
dTMyIGZtdCkKPiArewo+ICsJdTMyIGJ5dGVzX3Blcl9jb2w7Cj4gKwo+ICsJLyogcmF3IFJHQjg4
OCBvciBCR1I4ODggY2FuJ3QgYmUgcm90YXRlZCAqLwo+ICsJaWYgKChmbXQgPT0gRFJNX0ZPUk1B
VF9SR0I4ODgpIHx8IChmbXQgPT0gRFJNX0ZPUk1BVF9CR1I4ODgpKQo+ICsJCXJldHVybiAtRUlO
VkFMOwo+ICsKPiArCXN3aXRjaCAoZm10KSB7Cj4gKwkvKiA4IGxpbmVzIGF0IDQgYnl0ZXMgcGVy
IHBpeGVsICovCj4gKwljYXNlIERSTV9GT1JNQVRfQVJHQjIxMDEwMTA6Cj4gKwljYXNlIERSTV9G
T1JNQVRfQUJHUjIxMDEwMTA6Cj4gKwljYXNlIERSTV9GT1JNQVRfUkdCQTEwMTAxMDI6Cj4gKwlj
YXNlIERSTV9GT1JNQVRfQkdSQTEwMTAxMDI6Cj4gKwljYXNlIERSTV9GT1JNQVRfQVJHQjg4ODg6
Cj4gKwljYXNlIERSTV9GT1JNQVRfQUJHUjg4ODg6Cj4gKwljYXNlIERSTV9GT1JNQVRfUkdCQTg4
ODg6Cj4gKwljYXNlIERSTV9GT1JNQVRfQkdSQTg4ODg6Cj4gKwljYXNlIERSTV9GT1JNQVRfWFJH
Qjg4ODg6Cj4gKwljYXNlIERSTV9GT1JNQVRfWEJHUjg4ODg6Cj4gKwljYXNlIERSTV9GT1JNQVRf
UkdCWDg4ODg6Cj4gKwljYXNlIERSTV9GT1JNQVRfQkdSWDg4ODg6Cj4gKwljYXNlIERSTV9GT1JN
QVRfUkdCODg4Ogo+ICsJY2FzZSBEUk1fRk9STUFUX0JHUjg4ODoKPiArCS8qIDE2IGxpbmVzIGF0
IDIgYnl0ZXMgcGVyIHBpeGVsICovCj4gKwljYXNlIERSTV9GT1JNQVRfUkdCQTU1NTE6Cj4gKwlj
YXNlIERSTV9GT1JNQVRfQUJHUjE1NTU6Cj4gKwljYXNlIERSTV9GT1JNQVRfUkdCNTY1Ogo+ICsJ
Y2FzZSBEUk1fRk9STUFUX0JHUjU2NToKPiArCWNhc2UgRFJNX0ZPUk1BVF9VWVZZOgo+ICsJY2Fz
ZSBEUk1fRk9STUFUX1lVWVY6Cj4gKwkJYnl0ZXNfcGVyX2NvbCA9IDMyOwo+ICsJCWJyZWFrOwo+
ICsJLyogMTYgbGluZXMgYXQgMS41IGJ5dGVzIHBlciBwaXhlbCAqLwo+ICsJY2FzZSBEUk1fRk9S
TUFUX05WMTI6Cj4gKwljYXNlIERSTV9GT1JNQVRfWVVWNDIwOgo+ICsJCWJ5dGVzX3Blcl9jb2wg
PSAyNDsKPiArCQlicmVhazsKPiArCWRlZmF1bHQ6Cj4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gKwl9
Cj4gKwo+ICsJcmV0dXJuIHcgKiBieXRlc19wZXJfY29sOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW50
IG1hbGlkcDY1MF9xdWVyeV9odyhzdHJ1Y3QgbWFsaWRwX2h3X2RldmljZSAqaHdkZXYpCj4gK3sK
PiArCXUzMiBjb25mID0gbWFsaWRwX2h3X3JlYWQoaHdkZXYsIE1BTElEUDU1MF9DT05GSUdfSUQp
Owo+ICsJdTggbG5fc2l6ZSA9IChjb25mID4+IDQpICYgMHgzLCByc2l6ZTsKPiArCj4gKwlod2Rl
di0+bWluX2xpbmVfc2l6ZSA9IDQ7Cj4gKwo+ICsJc3dpdGNoIChsbl9zaXplKSB7Cj4gKwljYXNl
IDA6Cj4gKwljYXNlIDI6Cj4gKwkJLyogcmVzZXJ2ZWQgdmFsdWVzICovCj4gKwkJaHdkZXYtPm1h
eF9saW5lX3NpemUgPSAwOwo+ICsJCXJldHVybiAtRUlOVkFMOwo+ICsJY2FzZSAxOgo+ICsJCWh3
ZGV2LT5tYXhfbGluZV9zaXplID0gU1pfNEs7Cj4gKwkJLyogdHdvIGJhbmtzIG9mIDEyOEtCIGZv
ciByb3RhdGlvbiBtZW1vcnkgKi8KPiArCQlyc2l6ZSA9IDEyODsKPiArCQlicmVhazsKPiArCWNh
c2UgMzoKPiArCQlod2Rldi0+bWF4X2xpbmVfc2l6ZSA9IDI1NjA7Cj4gKwkJLyogdHdvIGJhbmtz
IG9mIDgwS0IgZm9yIHJvdGF0aW9uIG1lbW9yeSAqLwo+ICsJCXJzaXplID0gODA7Cj4gKwl9Cj4g
Kwo+ICsJaHdkZXYtPnJvdGF0aW9uX21lbW9yeVswXSA9IGh3ZGV2LT5yb3RhdGlvbl9tZW1vcnlb
MV0gPSByc2l6ZSAqIFNaXzFLOwo+ICsJcmV0dXJuIDA7Cj4gK30KPiArCj4gK2NvbnN0IHN0cnVj
dCBtYWxpZHBfaHdfZGV2aWNlIG1hbGlkcF9kZXZpY2VbTUFMSURQX01BWF9ERVZJQ0VTXSA9IHsK
PiArCVtNQUxJRFBfNTAwXSA9IHsKPiArCQkubWFwID0gewo+ICsJCQkuc2VfYmFzZSA9IE1BTElE
UDUwMF9TRV9CQVNFLAo+ICsJCQkuZGNfYmFzZSA9IE1BTElEUDUwMF9EQ19CQVNFLAo+ICsJCQku
ZGVfaXJxX21hcCA9IHsKPiArCQkJCS5pcnFfbWFzayA9IE1BTElEUF9ERV9JUlFfVU5ERVJSVU4g
fAo+ICsJCQkJCSAgICBNQUxJRFA1MDBfREVfSVJRX0FYSV9FUlIgfAo+ICsJCQkJCSAgICBNQUxJ
RFA1MDBfREVfSVJRX1ZTWU5DIHwKPiArCQkJCQkgICAgTUFMSURQNTAwX0RFX0lSUV9HTE9CQUws
Cj4gKwkJCQkudnN5bmNfaXJxID0gTUFMSURQNTAwX0RFX0lSUV9WU1lOQywKPiArCQkJfSwKPiAr
CQkJLnNlX2lycV9tYXAgPSB7Cj4gKwkJCQkuaXJxX21hc2sgPSBNQUxJRFA1MDBfU0VfSVJRX0NP
TkZfTU9ERSwKPiArCQkJCS52c3luY19pcnEgPSAwLAo+ICsJCQl9LAo+ICsJCQkuZGNfaXJxX21h
cCA9IHsKPiArCQkJCS5pcnFfbWFzayA9IE1BTElEUDUwMF9ERV9JUlFfQ09ORl9WQUxJRCwKPiAr
CQkJCS52c3luY19pcnEgPSBNQUxJRFA1MDBfREVfSVJRX0NPTkZfVkFMSUQsCj4gKwkJCX0sCj4g
KwkJCS5sYXllcnMgPSBtYWxpZHA1MDBfbGF5ZXJzLAo+ICsJCQkubl9sYXllcnMgPSBBUlJBWV9T
SVpFKG1hbGlkcDUwMF9sYXllcnMpLAo+ICsJCQkuaW5wdXRfZm9ybWF0cyA9IG1hbGlkcDUwMF9k
ZV9mb3JtYXRzLAo+ICsJCQkubl9pbnB1dF9mb3JtYXRzID0gQVJSQVlfU0laRShtYWxpZHA1MDBf
ZGVfZm9ybWF0cyksCj4gKwkJCS5vdXRfZGVwdGhfYmFzZSA9IE1BTElEUDUwMF9PVVRQVVRfREVQ
VEgsCj4gKwkJCS5mZWF0dXJlcyA9IDAsCS8qIG5vIENMRUFSSVJRIHJlZ2lzdGVyICovCj4gKwkJ
fSwKPiArCQkucXVlcnlfaHcgPSBtYWxpZHA1MDBfcXVlcnlfaHcsCj4gKwkJLmVudGVyX2NvbmZp
Z19tb2RlID0gbWFsaWRwNTAwX2VudGVyX2NvbmZpZ19tb2RlLAo+ICsJCS5sZWF2ZV9jb25maWdf
bW9kZSA9IG1hbGlkcDUwMF9sZWF2ZV9jb25maWdfbW9kZSwKPiArCQkuaW5fY29uZmlnX21vZGUg
PSBtYWxpZHA1MDBfaW5fY29uZmlnX21vZGUsCj4gKwkJLnNldF9jb25maWdfdmFsaWQgPSBtYWxp
ZHA1MDBfc2V0X2NvbmZpZ192YWxpZCwKPiArCQkubW9kZXNldCA9IG1hbGlkcDUwMF9tb2Rlc2V0
LAo+ICsJCS5yb3RtZW1fcmVxdWlyZWQgPSBtYWxpZHA1MDBfcm90bWVtX3JlcXVpcmVkLAo+ICsJ
fSwKPiArCVtNQUxJRFBfNTUwXSA9IHsKPiArCQkubWFwID0gewo+ICsJCQkuc2VfYmFzZSA9IE1B
TElEUDU1MF9TRV9CQVNFLAo+ICsJCQkuZGNfYmFzZSA9IE1BTElEUDU1MF9EQ19CQVNFLAo+ICsJ
CQkuZGVfaXJxX21hcCA9IHsKPiArCQkJCS5pcnFfbWFzayA9IE1BTElEUF9ERV9JUlFfVU5ERVJS
VU4gfAo+ICsJCQkJCSAgICBNQUxJRFA1NTBfREVfSVJRX1ZTWU5DLAo+ICsJCQkJLnZzeW5jX2ly
cSA9IE1BTElEUDU1MF9ERV9JUlFfVlNZTkMsCj4gKwkJCX0sCj4gKwkJCS5zZV9pcnFfbWFwID0g
ewo+ICsJCQkJLmlycV9tYXNrID0gTUFMSURQNTUwX1NFX0lSUV9FT1cgfAo+ICsJCQkJCSAgICBN
QUxJRFA1NTBfU0VfSVJRX0FYSV9FUlIsCj4gKwkJCX0sCj4gKwkJCS5kY19pcnFfbWFwID0gewo+
ICsJCQkJLmlycV9tYXNrID0gTUFMSURQNTUwX0RDX0lSUV9DT05GX1ZBTElELAo+ICsJCQkJLnZz
eW5jX2lycSA9IE1BTElEUDU1MF9EQ19JUlFfQ09ORl9WQUxJRCwKPiArCQkJfSwKPiArCQkJLmxh
eWVycyA9IG1hbGlkcDU1MF9sYXllcnMsCj4gKwkJCS5uX2xheWVycyA9IEFSUkFZX1NJWkUobWFs
aWRwNTUwX2xheWVycyksCj4gKwkJCS5pbnB1dF9mb3JtYXRzID0gbWFsaWRwNTUwX2RlX2Zvcm1h
dHMsCj4gKwkJCS5uX2lucHV0X2Zvcm1hdHMgPSBBUlJBWV9TSVpFKG1hbGlkcDU1MF9kZV9mb3Jt
YXRzKSwKPiArCQkJLm91dF9kZXB0aF9iYXNlID0gTUFMSURQNTUwX0RFX09VVFBVVF9ERVBUSCwK
PiArCQkJLmZlYXR1cmVzID0gTUFMSURQX1JFR01BUF9IQVNfQ0xFQVJJUlEsCj4gKwkJfSwKPiAr
CQkucXVlcnlfaHcgPSBtYWxpZHA1NTBfcXVlcnlfaHcsCj4gKwkJLmVudGVyX2NvbmZpZ19tb2Rl
ID0gbWFsaWRwNTUwX2VudGVyX2NvbmZpZ19tb2RlLAo+ICsJCS5sZWF2ZV9jb25maWdfbW9kZSA9
IG1hbGlkcDU1MF9sZWF2ZV9jb25maWdfbW9kZSwKPiArCQkuaW5fY29uZmlnX21vZGUgPSBtYWxp
ZHA1NTBfaW5fY29uZmlnX21vZGUsCj4gKwkJLnNldF9jb25maWdfdmFsaWQgPSBtYWxpZHA1NTBf
c2V0X2NvbmZpZ192YWxpZCwKPiArCQkubW9kZXNldCA9IG1hbGlkcDU1MF9tb2Rlc2V0LAo+ICsJ
CS5yb3RtZW1fcmVxdWlyZWQgPSBtYWxpZHA1NTBfcm90bWVtX3JlcXVpcmVkLAo+ICsJfSwKPiAr
CVtNQUxJRFBfNjUwXSA9IHsKPiArCQkubWFwID0gewo+ICsJCQkuc2VfYmFzZSA9IE1BTElEUDU1
MF9TRV9CQVNFLAo+ICsJCQkuZGNfYmFzZSA9IE1BTElEUDU1MF9EQ19CQVNFLAo+ICsJCQkuZGVf
aXJxX21hcCA9IHsKPiArCQkJCS5pcnFfbWFzayA9IE1BTElEUF9ERV9JUlFfVU5ERVJSVU4gfAo+
ICsJCQkJCSAgICBNQUxJRFA2NTBfREVfSVJRX0RSSUZUIHwKPiArCQkJCQkgICAgTUFMSURQNTUw
X0RFX0lSUV9WU1lOQywKPiArCQkJCS52c3luY19pcnEgPSBNQUxJRFA1NTBfREVfSVJRX1ZTWU5D
LAo+ICsJCQl9LAo+ICsJCQkuc2VfaXJxX21hcCA9IHsKPiArCQkJCS5pcnFfbWFzayA9IE1BTElE
UDU1MF9TRV9JUlFfRU9XIHwKPiArCQkJCQkgICAgTUFMSURQNTUwX1NFX0lSUV9BWElfRVJSLAo+
ICsJCQl9LAo+ICsJCQkuZGNfaXJxX21hcCA9IHsKPiArCQkJCS5pcnFfbWFzayA9IE1BTElEUDU1
MF9EQ19JUlFfQ09ORl9WQUxJRCwKPiArCQkJCS52c3luY19pcnEgPSBNQUxJRFA1NTBfRENfSVJR
X0NPTkZfVkFMSUQsCj4gKwkJCX0sCj4gKwkJCS5sYXllcnMgPSBtYWxpZHA1NTBfbGF5ZXJzLAo+
ICsJCQkubl9sYXllcnMgPSBBUlJBWV9TSVpFKG1hbGlkcDU1MF9sYXllcnMpLAo+ICsJCQkuaW5w
dXRfZm9ybWF0cyA9IG1hbGlkcDY1MF9kZV9mb3JtYXRzLAo+ICsJCQkubl9pbnB1dF9mb3JtYXRz
ID0gQVJSQVlfU0laRShtYWxpZHA2NTBfZGVfZm9ybWF0cyksCj4gKwkJCS5vdXRfZGVwdGhfYmFz
ZSA9IE1BTElEUDU1MF9ERV9PVVRQVVRfREVQVEgsCj4gKwkJCS5mZWF0dXJlcyA9IE1BTElEUF9S
RUdNQVBfSEFTX0NMRUFSSVJRLAo+ICsJCX0sCj4gKwkJLnF1ZXJ5X2h3ID0gbWFsaWRwNjUwX3F1
ZXJ5X2h3LAo+ICsJCS5lbnRlcl9jb25maWdfbW9kZSA9IG1hbGlkcDU1MF9lbnRlcl9jb25maWdf
bW9kZSwKPiArCQkubGVhdmVfY29uZmlnX21vZGUgPSBtYWxpZHA1NTBfbGVhdmVfY29uZmlnX21v
ZGUsCj4gKwkJLmluX2NvbmZpZ19tb2RlID0gbWFsaWRwNTUwX2luX2NvbmZpZ19tb2RlLAo+ICsJ
CS5zZXRfY29uZmlnX3ZhbGlkID0gbWFsaWRwNTUwX3NldF9jb25maWdfdmFsaWQsCj4gKwkJLm1v
ZGVzZXQgPSBtYWxpZHA1NTBfbW9kZXNldCwKPiArCQkucm90bWVtX3JlcXVpcmVkID0gbWFsaWRw
NTUwX3JvdG1lbV9yZXF1aXJlZCwKPiArCX0sCj4gK307Cj4gKwo+ICt1OCBtYWxpZHBfaHdfZ2V0
X2Zvcm1hdF9pZChjb25zdCBzdHJ1Y3QgbWFsaWRwX2h3X3JlZ21hcCAqbWFwLAo+ICsJCQkgICB1
OCBsYXllcl9pZCwgdTMyIGZvcm1hdCkKPiArewo+ICsJdW5zaWduZWQgaW50IGk7Cj4gKwo+ICsJ
Zm9yIChpID0gMDsgaSA8IG1hcC0+bl9pbnB1dF9mb3JtYXRzOyBpKyspIHsKPiArCQlpZiAoKCht
YXAtPmlucHV0X2Zvcm1hdHNbaV0ubGF5ZXIgJiBsYXllcl9pZCkgPT0gbGF5ZXJfaWQpICYmCj4g
KwkJICAgIChtYXAtPmlucHV0X2Zvcm1hdHNbaV0uZm9ybWF0ID09IGZvcm1hdCkpCj4gKwkJCXJl
dHVybiBtYXAtPmlucHV0X2Zvcm1hdHNbaV0uaWQ7Cj4gKwl9Cj4gKwo+ICsJcmV0dXJuICh1OCkt
MTsKPiArfQo+ICsKPiArCj4gK3UzMiBtYWxpZHBfaHdfcmVhZChzdHJ1Y3QgbWFsaWRwX2h3X2Rl
dmljZSAqaHdkZXYsIHUzMiByZWcpCj4gK3sKPiArCXUzMiB2YWx1ZSA9IHJlYWRsKGh3ZGV2LT5y
ZWdzICsgcmVnKTsKPiArCXJldHVybiB2YWx1ZTsKPiArfQo+ICsKPiArdm9pZCBtYWxpZHBfaHdf
d3JpdGUoc3RydWN0IG1hbGlkcF9od19kZXZpY2UgKmh3ZGV2LCB1MzIgdmFsdWUsIHUzMiByZWcp
Cj4gK3sKPiArCXdyaXRlbCh2YWx1ZSwgaHdkZXYtPnJlZ3MgKyByZWcpOwo+ICt9Cj4gKwo+ICt2
b2lkIG1hbGlkcF9od19zZXRiaXRzKHN0cnVjdCBtYWxpZHBfaHdfZGV2aWNlICpod2RldiwgdTMy
IG1hc2ssIHUzMiByZWcpCj4gK3sKPiArCXUzMiBkYXRhID0gbWFsaWRwX2h3X3JlYWQoaHdkZXYs
IHJlZyk7Cj4gKwo+ICsJZGF0YSB8PSBtYXNrOwo+ICsJbWFsaWRwX2h3X3dyaXRlKGh3ZGV2LCBk
YXRhLCByZWcpOwo+ICt9Cj4gKwo+ICt2b2lkIG1hbGlkcF9od19jbGVhcmJpdHMoc3RydWN0IG1h
bGlkcF9od19kZXZpY2UgKmh3ZGV2LCB1MzIgbWFzaywgdTMyIHJlZykKPiArewo+ICsJdTMyIGRh
dGEgPSBtYWxpZHBfaHdfcmVhZChod2RldiwgcmVnKTsKPiArCj4gKwlkYXRhICY9IH5tYXNrOwo+
ICsJbWFsaWRwX2h3X3dyaXRlKGh3ZGV2LCBkYXRhLCByZWcpOwo+ICt9Cj4gKwo+ICt2b2lkIG1h
bGlkcF9od19jbGVhcl9pcnEoc3RydWN0IG1hbGlkcF9od19kZXZpY2UgKmh3ZGV2LCB1OCBibG9j
aywgdTMyIGlycSkKPiArewo+ICsJdTMyIGJhc2UgPSAwOwo+ICsKPiArCXN3aXRjaCAoYmxvY2sp
IHsKPiArCWNhc2UgTUFMSURQX0RFX0JMT0NLOgo+ICsJCWJhc2UgPSAwOwo+ICsJCWJyZWFrOwo+
ICsJY2FzZSBNQUxJRFBfU0VfQkxPQ0s6Cj4gKwkJYmFzZSA9IGh3ZGV2LT5tYXAuc2VfYmFzZTsK
PiArCQlicmVhazsKPiArCWNhc2UgTUFMSURQX0RDX0JMT0NLOgo+ICsJCWJhc2UgPSBod2Rldi0+
bWFwLmRjX2Jhc2U7Cj4gKwkJYnJlYWs7Cj4gKwl9Cj4gKwo+ICsJaWYgKGh3ZGV2LT5tYXAuZmVh
dHVyZXMgJiBNQUxJRFBfUkVHTUFQX0hBU19DTEVBUklSUSkKPiArCQltYWxpZHBfaHdfd3JpdGUo
aHdkZXYsIGlycSwgYmFzZSArIE1BTElEUF9SRUdfQ0xFQVJJUlEpOwo+ICsJZWxzZQo+ICsJCW1h
bGlkcF9od193cml0ZShod2RldiwgaXJxLCBiYXNlICsgTUFMSURQX1JFR19TVEFUVVMpOwo+ICt9
Cj4gKwo+ICt2b2lkIG1hbGlkcF9od19kaXNhYmxlX2lycShzdHJ1Y3QgbWFsaWRwX2h3X2Rldmlj
ZSAqaHdkZXYsIHU4IGJsb2NrLCB1MzIgaXJxKQo+ICt7Cj4gKwl1MzIgYmFzZSA9IDA7Cj4gKwo+
ICsJc3dpdGNoIChibG9jaykgewo+ICsJY2FzZSBNQUxJRFBfREVfQkxPQ0s6Cj4gKwkJYmFzZSA9
IDA7Cj4gKwkJYnJlYWs7Cj4gKwljYXNlIE1BTElEUF9TRV9CTE9DSzoKPiArCQliYXNlID0gaHdk
ZXYtPm1hcC5zZV9iYXNlOwo+ICsJCWJyZWFrOwo+ICsJY2FzZSBNQUxJRFBfRENfQkxPQ0s6Cj4g
KwkJYmFzZSA9IGh3ZGV2LT5tYXAuZGNfYmFzZTsKPiArCQlicmVhazsKPiArCX0KPiArCj4gKwlt
YWxpZHBfaHdfY2xlYXJiaXRzKGh3ZGV2LCBpcnEsIGJhc2UgKyBNQUxJRFBfUkVHX01BU0tJUlEp
Owo+ICt9Cj4gKwo+ICt2b2lkIG1hbGlkcF9od19lbmFibGVfaXJxKHN0cnVjdCBtYWxpZHBfaHdf
ZGV2aWNlICpod2RldiwgdTggYmxvY2ssIHUzMiBpcnEpCj4gK3sKPiArCXUzMiBiYXNlID0gMDsK
PiArCj4gKwlzd2l0Y2ggKGJsb2NrKSB7Cj4gKwljYXNlIE1BTElEUF9ERV9CTE9DSzoKPiArCQli
YXNlID0gMDsKPiArCQlicmVhazsKPiArCWNhc2UgTUFMSURQX1NFX0JMT0NLOgo+ICsJCWJhc2Ug
PSBod2Rldi0+bWFwLnNlX2Jhc2U7Cj4gKwkJYnJlYWs7Cj4gKwljYXNlIE1BTElEUF9EQ19CTE9D
SzoKPiArCQliYXNlID0gaHdkZXYtPm1hcC5kY19iYXNlOwo+ICsJCWJyZWFrOwo+ICsJfQo+ICsK
PiArCW1hbGlkcF9od19zZXRiaXRzKGh3ZGV2LCBpcnEsIGJhc2UgKyBNQUxJRFBfUkVHX01BU0tJ
UlEpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaXJxcmV0dXJuX3QgbWFsaWRwX2RlX2lycShpbnQgaXJx
LCB2b2lkICphcmcpCj4gK3sKPiArCXN0cnVjdCBkcm1fZGV2aWNlICpkcm0gPSBhcmc7Cj4gKwlz
dHJ1Y3QgbWFsaWRwX2RybSAqbWFsaWRwID0gZHJtLT5kZXZfcHJpdmF0ZTsKPiArCXN0cnVjdCBt
YWxpZHBfaHdfZGV2aWNlICpod2RldjsKPiArCWNvbnN0IHN0cnVjdCBtYWxpZHBfaXJxX21hcCAq
ZGU7Cj4gKwl1MzIgc3RhdHVzLCBtYXNrLCBkY19zdGF0dXM7Cj4gKwlpcnFyZXR1cm5fdCByZXQg
PSBJUlFfTk9ORTsKPiArCj4gKwlpZiAoIWRybS0+ZGV2X3ByaXZhdGUpCj4gKwkJcmV0dXJuIElS
UV9IQU5ETEVEOwo+ICsKPiArCWh3ZGV2ID0gbWFsaWRwLT5kZXY7Cj4gKwlkZSA9ICZod2Rldi0+
bWFwLmRlX2lycV9tYXA7Cj4gKwo+ICsJLyogZmlyc3QgaGFuZGxlIHRoZSBjb25maWcgdmFsaWQg
SVJRICovCj4gKwlkY19zdGF0dXMgPSBtYWxpZHBfaHdfcmVhZChod2RldiwgaHdkZXYtPm1hcC5k
Y19iYXNlICsgTUFMSURQX1JFR19TVEFUVVMpOwo+ICsJaWYgKGRjX3N0YXR1cyAmIGh3ZGV2LT5t
YXAuZGNfaXJxX21hcC52c3luY19pcnEpIHsKPiArCQkvKiB3ZSBoYXZlIGEgcGFnZSBmbGlwIGV2
ZW50ICovCj4gKwkJYXRvbWljX3NldCgmbWFsaWRwLT5jb25maWdfdmFsaWQsIDEpOwo+ICsJCW1h
bGlkcF9od19jbGVhcl9pcnEoaHdkZXYsIE1BTElEUF9EQ19CTE9DSywgZGNfc3RhdHVzKTsKPiAr
CQlyZXQgPSBJUlFfV0FLRV9USFJFQUQ7Cj4gKwl9Cj4gKwo+ICsJc3RhdHVzID0gbWFsaWRwX2h3
X3JlYWQoaHdkZXYsIE1BTElEUF9SRUdfU1RBVFVTKTsKPiArCWlmICghKHN0YXR1cyAmIGRlLT5p
cnFfbWFzaykpCj4gKwkJcmV0dXJuIHJldDsKPiArCj4gKwltYXNrID0gbWFsaWRwX2h3X3JlYWQo
aHdkZXYsIE1BTElEUF9SRUdfTUFTS0lSUSk7Cj4gKwlzdGF0dXMgJj0gbWFzazsKPiArCWlmIChz
dGF0dXMgJiBkZS0+dnN5bmNfaXJxKQo+ICsJCWRybV9jcnRjX2hhbmRsZV92YmxhbmsoJm1hbGlk
cC0+Y3J0Yyk7Cj4gKwo+ICsJbWFsaWRwX2h3X2NsZWFyX2lycShod2RldiwgTUFMSURQX0RFX0JM
T0NLLCBzdGF0dXMpOwo+ICsKPiArCXJldHVybiAocmV0ID09IElSUV9OT05FKSA/IElSUV9IQU5E
TEVEIDogcmV0Owo+ICt9Cj4gKwo+ICtzdGF0aWMgaXJxcmV0dXJuX3QgbWFsaWRwX2RlX2lycV90
aHJlYWRfaGFuZGxlcihpbnQgaXJxLCB2b2lkICphcmcpCj4gK3sKPiArCXN0cnVjdCBkcm1fZGV2
aWNlICpkcm0gPSBhcmc7Cj4gKwlzdHJ1Y3QgbWFsaWRwX2RybSAqbWFsaWRwID0gZHJtLT5kZXZf
cHJpdmF0ZTsKPiArCj4gKwl3YWtlX3VwKCZtYWxpZHAtPndxKTsKPiArCj4gKwlyZXR1cm4gSVJR
X0hBTkRMRUQ7Cj4gK30KPiArCj4gK2ludCBtYWxpZHBfZGVfaXJxX2luaXQoc3RydWN0IGRybV9k
ZXZpY2UgKmRybSwgaW50IGlycSkKPiArewo+ICsJc3RydWN0IG1hbGlkcF9kcm0gKm1hbGlkcCA9
IGRybS0+ZGV2X3ByaXZhdGU7Cj4gKwlzdHJ1Y3QgbWFsaWRwX2h3X2RldmljZSAqaHdkZXYgPSBt
YWxpZHAtPmRldjsKPiArCWludCByZXQ7Cj4gKwo+ICsJLyogZW5zdXJlIGludGVycnVwdHMgYXJl
IGRpc2FibGVkICovCj4gKwltYWxpZHBfaHdfZGlzYWJsZV9pcnEoaHdkZXYsIE1BTElEUF9EQ19C
TE9DSywgMHhmZmZmZmZmZik7Cj4gKwltYWxpZHBfaHdfY2xlYXJfaXJxKGh3ZGV2LCBNQUxJRFBf
RENfQkxPQ0ssIDB4ZmZmZmZmZmYpOwo+ICsJbWFsaWRwX2h3X2Rpc2FibGVfaXJxKGh3ZGV2LCBN
QUxJRFBfREVfQkxPQ0ssIDB4ZmZmZmZmZmYpOwo+ICsJbWFsaWRwX2h3X2NsZWFyX2lycShod2Rl
diwgTUFMSURQX0RFX0JMT0NLLCAweGZmZmZmZmZmKTsKPiArCj4gKwlyZXQgPSBkZXZtX3JlcXVl
c3RfdGhyZWFkZWRfaXJxKGRybS0+ZGV2LCBpcnEsIG1hbGlkcF9kZV9pcnEsCj4gKwkJCQkJbWFs
aWRwX2RlX2lycV90aHJlYWRfaGFuZGxlciwKPiArCQkJCQlJUlFGX1NIQVJFRCwgIm1hbGlkcC1k
ZSIsIGRybSk7Cj4gKwlpZiAocmV0IDwgMCkgewo+ICsJCURSTV9FUlJPUigiZmFpbGVkIHRvIGlu
c3RhbGwgREUgSVJRIGhhbmRsZXJcbiIpOwo+ICsJCXJldHVybiByZXQ7Cj4gKwl9Cj4gKwo+ICsJ
LyogZmlyc3QgZW5hYmxlIHRoZSBEQyBibG9jayBJUlFzICovCj4gKwltYWxpZHBfaHdfZW5hYmxl
X2lycShod2RldiwgTUFMSURQX0RDX0JMT0NLLAo+ICsJCQkgICAgIGh3ZGV2LT5tYXAuZGNfaXJx
X21hcC5pcnFfbWFzayk7Cj4gKwo+ICsJLyogbm93IGVuYWJsZSB0aGUgREUgYmxvY2sgSVJRcyAq
Lwo+ICsJbWFsaWRwX2h3X2VuYWJsZV9pcnEoaHdkZXYsIE1BTElEUF9ERV9CTE9DSywKPiArCQkJ
ICAgICBod2Rldi0+bWFwLmRlX2lycV9tYXAuaXJxX21hc2spOwo+ICsKPiArCXJldHVybiAwOwo+
ICt9Cj4gKwo+ICt2b2lkIG1hbGlkcF9kZV9pcnFfY2xlYW51cChzdHJ1Y3QgZHJtX2RldmljZSAq
ZHJtKQo+ICt7Cj4gKwlzdHJ1Y3QgbWFsaWRwX2RybSAqbWFsaWRwID0gZHJtLT5kZXZfcHJpdmF0
ZTsKPiArCXN0cnVjdCBtYWxpZHBfaHdfZGV2aWNlICpod2RldiA9IG1hbGlkcC0+ZGV2Owo+ICsK
PiArCW1hbGlkcF9od19kaXNhYmxlX2lycShod2RldiwgTUFMSURQX0RFX0JMT0NLLAo+ICsJCQkg
ICAgICBod2Rldi0+bWFwLmRlX2lycV9tYXAuaXJxX21hc2spOwo+ICsJbWFsaWRwX2h3X2Rpc2Fi
bGVfaXJxKGh3ZGV2LCBNQUxJRFBfRENfQkxPQ0ssCj4gKwkJCSAgICAgIGh3ZGV2LT5tYXAuZGNf
aXJxX21hcC5pcnFfbWFzayk7Cj4gK30KPiArCj4gK3N0YXRpYyBpcnFyZXR1cm5fdCBtYWxpZHBf
c2VfaXJxKGludCBpcnEsIHZvaWQgKmFyZykKPiArewo+ICsJc3RydWN0IGRybV9kZXZpY2UgKmRy
bSA9IGFyZzsKPiArCXN0cnVjdCBtYWxpZHBfZHJtICptYWxpZHAgPSBkcm0tPmRldl9wcml2YXRl
Owo+ICsJc3RydWN0IG1hbGlkcF9od19kZXZpY2UgKmh3ZGV2ID0gbWFsaWRwLT5kZXY7Cj4gKwl1
MzIgc3RhdHVzLCBtYXNrOwo+ICsKPiArCXN0YXR1cyA9IG1hbGlkcF9od19yZWFkKGh3ZGV2LCBo
d2Rldi0+bWFwLnNlX2Jhc2UgKyBNQUxJRFBfUkVHX1NUQVRVUyk7Cj4gKwlpZiAoIShzdGF0dXMg
JiBod2Rldi0+bWFwLnNlX2lycV9tYXAuaXJxX21hc2spKQo+ICsJCXJldHVybiBJUlFfTk9ORTsK
PiArCj4gKwltYXNrID0gbWFsaWRwX2h3X3JlYWQoaHdkZXYsIGh3ZGV2LT5tYXAuc2VfYmFzZSAr
IE1BTElEUF9SRUdfTUFTS0lSUSk7Cj4gKwlzdGF0dXMgPSBtYWxpZHBfaHdfcmVhZChod2Rldiwg
aHdkZXYtPm1hcC5zZV9iYXNlICsgTUFMSURQX1JFR19TVEFUVVMpOwo+ICsJc3RhdHVzICY9IG1h
c2s7Cj4gKwkvKiBUb0RvOiBzdGF0dXMgZGVjb2RpbmcgYW5kIGZpcmluZyB1cCBvZiBWU1lOQyBh
bmQgcGFnZSBmbGlwIGV2ZW50cyAqLwo+ICsKPiArCW1hbGlkcF9od19jbGVhcl9pcnEoaHdkZXYs
IE1BTElEUF9TRV9CTE9DSywgc3RhdHVzKTsKPiArCS8qIHJldHVybiBJUlFfV0FLRV9USFJFQUQ7
ICovCj4gKwlyZXR1cm4gSVJRX0hBTkRMRUQ7Cj4gK30KPiArCj4gK3N0YXRpYyBpcnFyZXR1cm5f
dCBtYWxpZHBfc2VfaXJxX3RocmVhZF9oYW5kbGVyKGludCBpcnEsIHZvaWQgKmFyZykKPiArewo+
ICsJcmV0dXJuIElSUV9IQU5ETEVEOwo+ICt9Cj4gKwo+ICtpbnQgbWFsaWRwX3NlX2lycV9pbml0
KHN0cnVjdCBkcm1fZGV2aWNlICpkcm0sIGludCBpcnEpCj4gK3sKPiArCXN0cnVjdCBtYWxpZHBf
ZHJtICptYWxpZHAgPSBkcm0tPmRldl9wcml2YXRlOwo+ICsJc3RydWN0IG1hbGlkcF9od19kZXZp
Y2UgKmh3ZGV2ID0gbWFsaWRwLT5kZXY7Cj4gKwlpbnQgcmV0Owo+ICsKPiArCS8qIGVuc3VyZSBp
bnRlcnJ1cHRzIGFyZSBkaXNhYmxlZCAqLwo+ICsJbWFsaWRwX2h3X2Rpc2FibGVfaXJxKGh3ZGV2
LCBNQUxJRFBfU0VfQkxPQ0ssIDB4ZmZmZmZmZmYpOwo+ICsJbWFsaWRwX2h3X2NsZWFyX2lycSho
d2RldiwgTUFMSURQX1NFX0JMT0NLLCAweGZmZmZmZmZmKTsKPiArCj4gKwlyZXQgPSBkZXZtX3Jl
cXVlc3RfdGhyZWFkZWRfaXJxKGRybS0+ZGV2LCBpcnEsIG1hbGlkcF9zZV9pcnEsCj4gKwkJCQkJ
bWFsaWRwX3NlX2lycV90aHJlYWRfaGFuZGxlciwKPiArCQkJCQlJUlFGX1NIQVJFRCwgIm1hbGlk
cC1zZSIsIGRybSk7Cj4gKwlpZiAocmV0IDwgMCkgewo+ICsJCURSTV9FUlJPUigiZmFpbGVkIHRv
IGluc3RhbGwgU0UgSVJRIGhhbmRsZXJcbiIpOwo+ICsJCXJldHVybiByZXQ7Cj4gKwl9Cj4gKwo+
ICsJbWFsaWRwX2h3X2VuYWJsZV9pcnEoaHdkZXYsIE1BTElEUF9TRV9CTE9DSywKPiArCQkJICAg
ICBod2Rldi0+bWFwLnNlX2lycV9tYXAuaXJxX21hc2spOwo+ICsKPiArCXJldHVybiAwOwo+ICt9
Cj4gKwo+ICt2b2lkIG1hbGlkcF9zZV9pcnFfY2xlYW51cChzdHJ1Y3QgZHJtX2RldmljZSAqZHJt
KQo+ICt7Cj4gKwlzdHJ1Y3QgbWFsaWRwX2RybSAqbWFsaWRwID0gZHJtLT5kZXZfcHJpdmF0ZTsK
PiArCXN0cnVjdCBtYWxpZHBfaHdfZGV2aWNlICpod2RldiA9IG1hbGlkcC0+ZGV2Owo+ICsKPiAr
CW1hbGlkcF9od19kaXNhYmxlX2lycShod2RldiwgTUFMSURQX1NFX0JMT0NLLAo+ICsJCQkgICAg
ICBod2Rldi0+bWFwLnNlX2lycV9tYXAuaXJxX21hc2spOwo+ICt9Cj4gZGlmZiAtLWdpdCBhL2Ry
aXZlcnMvZ3B1L2RybS9hcm0vbWFsaWRwX2h3LmggYi9kcml2ZXJzL2dwdS9kcm0vYXJtL21hbGlk
cF9ody5oCj4gbmV3IGZpbGUgbW9kZSAxMDA2NDQKPiBpbmRleCAwMDAwMDAwLi5mYWIxZmU3Cj4g
LS0tIC9kZXYvbnVsbAo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9hcm0vbWFsaWRwX2h3LmgKPiBA
QCAtMCwwICsxLDE4OSBAQAo+ICsvKgo+ICsgKgo+ICsgKiAoQykgQ09QWVJJR0hUIDIwMTMtMjAx
NiBBUk0gTGltaXRlZC4gQWxsIHJpZ2h0cyByZXNlcnZlZC4KPiArICoKPiArICogVGhpcyBwcm9n
cmFtIGlzIGZyZWUgc29mdHdhcmUgYW5kIGlzIHByb3ZpZGVkIHRvIHlvdSB1bmRlciB0aGUgdGVy
bXMgb2YgdGhlCj4gKyAqIEdOVSBHZW5lcmFsIFB1YmxpYyBMaWNlbnNlIHZlcnNpb24gMiBhcyBw
dWJsaXNoZWQgYnkgdGhlIEZyZWUgU29mdHdhcmUKPiArICogRm91bmRhdGlvbiwgYW5kIGFueSB1
c2UgYnkgeW91IG9mIHRoaXMgcHJvZ3JhbSBpcyBzdWJqZWN0IHRvIHRoZSB0ZXJtcwo+ICsgKiBv
ZiBzdWNoIEdOVSBsaWNlbmNlLgo+ICsgKgo+ICsgKiBBUk0gTWFsaSBEUCBoYXJkd2FyZSBtYW5p
cHVsYXRpb24gcm91dGluZXMuCj4gKyAqLwo+ICsKPiArI2lmbmRlZiBfX01BTElEUF9IV19IX18K
PiArI2RlZmluZSBfX01BTElEUF9IV19IX18KPiArCj4gKyNpbmNsdWRlIDxkcm0vZHJtX2ZvdXJj
Yy5oPgo+ICsjaW5jbHVkZSA8bGludXgvYml0b3BzLmg+Cj4gKwo+ICtzdHJ1Y3QgdmlkZW9tb2Rl
Owo+ICtzdHJ1Y3QgY2xrOwo+ICsKPiArLyogTWFsaSBEUCBJUCBibG9ja3MgKi8KPiArZW51bSB7
Cj4gKwlNQUxJRFBfREVfQkxPQ0sgPSAwLAo+ICsJTUFMSURQX1NFX0JMT0NLLAo+ICsJTUFMSURQ
X0RDX0JMT0NLCj4gK307Cj4gKwo+ICsvKiBNYWxpIERQIGxheWVyIElEcyAqLwo+ICtlbnVtIHsK
PiArCURFX1ZJREVPMSA9IEJJVCgwKSwKPiArCURFX0dSQVBISUNTMSA9IEJJVCgxKSwKPiArCURF
X0dSQVBISUNTMiA9IEJJVCgyKSwgLyogdXNlZCBvbmx5IGluIERQNTAwICovCj4gKwlERV9WSURF
TzIgPSBCSVQoMyksCj4gKwlERV9TTUFSVCA9IEJJVCg0KSwKPiArfTsKPiArCj4gK3N0cnVjdCBt
YWxpZHBfaW5wdXRfZm9ybWF0IHsKPiArCXU4IGxheWVyOwkJLyogYml0bWFzayBvZiBsYXllcnMg
c3VwcG9ydGluZyBpdCAqLwo+ICsJdTggaWQ7CQkJLyogdXNlZCBpbnRlcm5hbGx5ICovCj4gKwl1
MzIgZm9ybWF0OwkJLyogRFJNIGZvdXJjYyAqLwo+ICt9Owo+ICsKPiArLyoKPiArICogaGlkZSB0
aGUgZGlmZmVyZW5jZXMgYmV0d2VlbiByZWdpc3RlciBtYXBzCj4gKyAqIGJ5IHVzaW5nIGEgY29t
bW9uIHN0cnVjdHVyZSB0byBob2xkIHRoZQo+ICsgKiBiYXNlIHJlZ2lzdGVyIG9mZnNldHMKPiAr
ICovCj4gKwo+ICtzdHJ1Y3QgbWFsaWRwX2lycV9tYXAgewo+ICsJdTMyIGlycV9tYXNrOwkJLyog
bWFzayBvZiBJUlFzIHRoYXQgY2FuIGJlIGVuYWJsZWQgaW4gdGhlIGJsb2NrICovCj4gKwl1MzIg
dnN5bmNfaXJxOwkJLyogSVJRIGJpdCB1c2VkIGZvciBzaWduYWxpbmcgZHVyaW5nIFZTWU5DICov
Cj4gK307Cj4gKwo+ICtzdHJ1Y3QgbWFsaWRwX2xheWVyIHsKPiArCXU4IGlkOwkJCS8qIGxheWVy
IElEICovCj4gKwl1MTYgYmFzZTsJCS8qIGFkZHJlc3Mgb2Zmc2V0IGZvciB0aGUgcmVnaXN0ZXIg
YmFuayAqLwo+ICsJdTE2IHB0cjsJCS8qIGFkZHJlc3Mgb2Zmc2V0IGZvciB0aGUgcG9pbnRlciBy
ZWdpc3RlciAqLwo+ICt9Owo+ICsKPiArLyogcmVnbWFwIGZlYXR1cmVzICovCj4gKyNkZWZpbmUg
TUFMSURQX1JFR01BUF9IQVNfQ0xFQVJJUlEJKDEgPDwgMCkKPiArCj4gK3N0cnVjdCBtYWxpZHBf
aHdfcmVnbWFwIHsKPiArCS8qIGFkZHJlc3Mgb2Zmc2V0IG9mIHRoZSBERSByZWdpc3RlciBiYW5r
ICovCj4gKwkvKiBpcyBhbHdheXMgMHgwMDAwICovCj4gKwkvKiBhZGRyZXNzIG9mZnNldCBvZiB0
aGUgU0UgcmVnaXN0ZXJzIGJhbmsgKi8KPiArCWNvbnN0IHUxNiBzZV9iYXNlOwo+ICsJLyogYWRk
cmVzcyBvZmZzZXQgb2YgdGhlIERDIHJlZ2lzdGVycyBiYW5rICovCj4gKwljb25zdCB1MTYgZGNf
YmFzZTsKPiArCj4gKwljb25zdCBzdHJ1Y3QgbWFsaWRwX2lycV9tYXAgZGVfaXJxX21hcDsKPiAr
CWNvbnN0IHN0cnVjdCBtYWxpZHBfaXJxX21hcCBzZV9pcnFfbWFwOwo+ICsJY29uc3Qgc3RydWN0
IG1hbGlkcF9pcnFfbWFwIGRjX2lycV9tYXA7Cj4gKwo+ICsJLyogbGlzdCBvZiBzdXBwb3J0ZWQg
bGF5ZXJzICovCj4gKwljb25zdCBzdHJ1Y3QgbWFsaWRwX2xheWVyICpsYXllcnM7Cj4gKwljb25z
dCB1OCBuX2xheWVyczsKPiArCj4gKwkvKiBsaXN0IG9mIHN1cHBvcnRlZCBpbnB1dCBmb3JtYXRz
IGZvciBlYWNoIGxheWVyICovCj4gKwljb25zdCBzdHJ1Y3QgbWFsaWRwX2lucHV0X2Zvcm1hdCAq
aW5wdXRfZm9ybWF0czsKPiArCWNvbnN0IHU4IG5faW5wdXRfZm9ybWF0czsKPiArCj4gKwkvKiBh
ZGRyZXNzIG9mZnNldCBmb3IgdGhlIG91dHB1dCBkZXB0aCByZWdpc3RlciAqLwo+ICsJY29uc3Qg
dTE2IG91dF9kZXB0aF9iYXNlOwo+ICsKPiArCS8qIGJpdG1hcCB3aXRoIHJlZ2lzdGVyIG1hcCBm
ZWF0dXJlcyAqLwo+ICsJY29uc3QgdTggZmVhdHVyZXM7Cj4gK307Cj4gKwo+ICtzdHJ1Y3QgbWFs
aWRwX2h3X2RldmljZSB7Cj4gKwljb25zdCBzdHJ1Y3QgbWFsaWRwX2h3X3JlZ21hcCBtYXA7Cj4g
Kwl2b2lkIF9faW9tZW0gKnJlZ3M7Cj4gKwo+ICsJLyogQVBCIGNsb2NrICovCj4gKwlzdHJ1Y3Qg
Y2xrICpwY2xrOwo+ICsJLyogQVhJIGNsb2NrICovCj4gKwlzdHJ1Y3QgY2xrICphY2xrOwo+ICsJ
LyogbWFpbiBjbG9jayBmb3IgZGlzcGxheSBjb3JlICovCj4gKwlzdHJ1Y3QgY2xrICptY2xrOwo+
ICsJLyogcGl4ZWwgY2xvY2sgZm9yIGRpc3BsYXkgY29yZSAqLwo+ICsJc3RydWN0IGNsayAqcHhs
Y2xrOwo+ICsKPiArCS8qCj4gKwkgKiBWYWxpZGF0ZSB0aGUgZHJpdmVyIGluc3RhbmNlIGFnYWlu
c3QgdGhlIGhhcmR3YXJlIGJpdHMKPiArCSAqLwo+ICsJaW50ICgqcXVlcnlfaHcpKHN0cnVjdCBt
YWxpZHBfaHdfZGV2aWNlICpod2Rldik7Cj4gKwo+ICsJLyoKPiArCSAqIFNldCB0aGUgaGFyZHdh
cmUgaW50byBjb25maWcgbW9kZSwgcmVhZHkgdG8gYWNjZXB0IG1vZGUgY2hhbmdlcwo+ICsJICov
Cj4gKwl2b2lkICgqZW50ZXJfY29uZmlnX21vZGUpKHN0cnVjdCBtYWxpZHBfaHdfZGV2aWNlICpo
d2Rldik7Cj4gKwo+ICsJLyoKPiArCSAqIFRlbGwgaGFyZHdhcmUgdG8gZXhpdCBjb25maWd1cmF0
aW9uIG1vZGUKPiArCSAqLwo+ICsJdm9pZCAoKmxlYXZlX2NvbmZpZ19tb2RlKShzdHJ1Y3QgbWFs
aWRwX2h3X2RldmljZSAqaHdkZXYpOwo+ICsKPiArCS8qCj4gKwkgKiBRdWVyeSBpZiBoYXJkd2Fy
ZSBpcyBpbiBjb25maWd1cmF0aW9uIG1vZGUKPiArCSAqLwo+ICsJYm9vbCAoKmluX2NvbmZpZ19t
b2RlKShzdHJ1Y3QgbWFsaWRwX2h3X2RldmljZSAqaHdkZXYpOwo+ICsKPiArCS8qCj4gKwkgKiBT
ZXQgY29uZmlndXJhdGlvbiB2YWxpZCBmbGFnIGZvciBoYXJkd2FyZSBwYXJhbWV0ZXJzIHRoYXQg
Y2FuCj4gKwkgKiBiZSBjaGFuZ2VkIG91dHNpZGUgdGhlIGNvbmZpZ3VyYXRpb24gbW9kZS4gSGFy
ZHdhcmUgd2lsbCB1c2UKPiArCSAqIHRoZSBuZXcgc2V0dGluZ3Mgd2hlbiBjb25maWcgdmFsaWQg
aXMgc2V0IGFmdGVyIHRoZSBlbmQgb2YgdGhlCj4gKwkgKiBjdXJyZW50IGJ1ZmZlciBzY2Fub3V0
Cj4gKwkgKi8KPiArCXZvaWQgKCpzZXRfY29uZmlnX3ZhbGlkKShzdHJ1Y3QgbWFsaWRwX2h3X2Rl
dmljZSAqaHdkZXYpOwo+ICsKPiArCS8qCj4gKwkgKiBTZXQgYSBuZXcgbW9kZSBpbiBoYXJkd2Fy
ZS4gUmVxdWlyZXMgdGhlIGhhcmR3YXJlIHRvIGJlIGluCj4gKwkgKiBjb25maWd1cmF0aW9uIG1v
ZGUgYmVmb3JlIHRoaXMgZnVuY3Rpb24gaXMgY2FsbGVkLgo+ICsJICovCj4gKwl2b2lkICgqbW9k
ZXNldCkoc3RydWN0IG1hbGlkcF9od19kZXZpY2UgKmh3ZGV2LCBzdHJ1Y3QgdmlkZW9tb2RlICpt
KTsKPiArCj4gKwkvKgo+ICsJICogQ2FsY3VsYXRlIHRoZSByZXF1aXJlZCByb3RhdGlvbiBtZW1v
cnkgZ2l2ZW4gdGhlIGFjdGl2ZSBhcmVhCj4gKwkgKiBhbmQgdGhlIGJ1ZmZlciBmb3JtYXQuCj4g
KwkgKi8KPiArCWludCAoKnJvdG1lbV9yZXF1aXJlZCkoc3RydWN0IG1hbGlkcF9od19kZXZpY2Ug
Kmh3ZGV2LCB1MTYgdywgdTE2IGgsIHUzMiBmbXQpOwo+ICsKPiArCXU4IGZlYXR1cmVzOwo+ICsK
PiArCXU4IG1pbl9saW5lX3NpemU7Cj4gKwl1MTYgbWF4X2xpbmVfc2l6ZTsKPiArCj4gKwkvKiBz
aXplIG9mIG1lbW9yeSB1c2VkIGZvciByb3RhdGluZyBsYXllcnMsIHVwIHRvIHR3byBiYW5rcyBh
dmFpbGFibGUgKi8KPiArCXUzMiByb3RhdGlvbl9tZW1vcnlbMl07Cj4gK307Cj4gKwo+ICsvKiBT
dXBwb3J0ZWQgdmFyaWFudHMgb2YgdGhlIGhhcmR3YXJlICovCj4gK2VudW0gewo+ICsJTUFMSURQ
XzUwMCA9IDAsCj4gKwlNQUxJRFBfNTUwLAo+ICsJTUFMSURQXzY1MCwKPiArCS8qIGtlZXAgdGhl
IG5leHQgZW50cnkgbGFzdCAqLwo+ICsJTUFMSURQX01BWF9ERVZJQ0VTCj4gK307Cj4gKwo+ICtl
eHRlcm4gY29uc3Qgc3RydWN0IG1hbGlkcF9od19kZXZpY2UgbWFsaWRwX2RldmljZVtNQUxJRFBf
TUFYX0RFVklDRVNdOwo+ICsKPiArdTMyIG1hbGlkcF9od19yZWFkKHN0cnVjdCBtYWxpZHBfaHdf
ZGV2aWNlICpod2RldiwgdTMyIHJlZyk7Cj4gK3ZvaWQgbWFsaWRwX2h3X3dyaXRlKHN0cnVjdCBt
YWxpZHBfaHdfZGV2aWNlICpod2RldiwgdTMyIHZhbHVlLCB1MzIgcmVnKTsKPiArdm9pZCBtYWxp
ZHBfaHdfc2V0Yml0cyhzdHJ1Y3QgbWFsaWRwX2h3X2RldmljZSAqaHdkZXYsIHUzMiBtYXNrLCB1
MzIgcmVnKTsKPiArdm9pZCBtYWxpZHBfaHdfY2xlYXJiaXRzKHN0cnVjdCBtYWxpZHBfaHdfZGV2
aWNlICpod2RldiwgdTMyIG1hc2ssIHUzMiByZWcpOwo+ICt2b2lkIG1hbGlkcF9od19jbGVhcl9p
cnEoc3RydWN0IG1hbGlkcF9od19kZXZpY2UgKmh3ZGV2LCB1OCBibG9jaywgdTMyIGlycSk7Cj4g
K3ZvaWQgbWFsaWRwX2h3X2Rpc2FibGVfaXJxKHN0cnVjdCBtYWxpZHBfaHdfZGV2aWNlICpod2Rl
diwgdTggYmxvY2ssIHUzMiBpcnEpOwo+ICt2b2lkIG1hbGlkcF9od19lbmFibGVfaXJxKHN0cnVj
dCBtYWxpZHBfaHdfZGV2aWNlICpod2RldiwgdTggYmxvY2ssIHUzMiBpcnEpOwo+ICsKPiAraW50
IG1hbGlkcF9kZV9pcnFfaW5pdChzdHJ1Y3QgZHJtX2RldmljZSAqZHJtLCBpbnQgaXJxKTsKPiAr
aW50IG1hbGlkcF9zZV9pcnFfaW5pdChzdHJ1Y3QgZHJtX2RldmljZSAqZHJtLCBpbnQgaXJxKTsK
PiArdm9pZCBtYWxpZHBfZGVfaXJxX2NsZWFudXAoc3RydWN0IGRybV9kZXZpY2UgKmRybSk7Cj4g
K3ZvaWQgbWFsaWRwX3NlX2lycV9jbGVhbnVwKHN0cnVjdCBkcm1fZGV2aWNlICpkcm0pOwo+ICsK
PiArdTggbWFsaWRwX2h3X2dldF9mb3JtYXRfaWQoY29uc3Qgc3RydWN0IG1hbGlkcF9od19yZWdt
YXAgKm1hcCwKPiArCQkJICAgdTggbGF5ZXJfaWQsIHUzMiBmb3JtYXQpOwo+ICsKPiArLyoKPiAr
ICogYmFja2dyb3VuZCBjb2xvciBjb21wb25lbnRzIGFyZSBkZWZpbmVkIGFzIDEyYml0cyB2YWx1
ZXMsCj4gKyAqIHRoZXkgd2lsbCBiZSBzaGlmdGVkIHJpZ2h0IHdoZW4gc3RvcmVkIG9uIGhhcmR3
YXJlIHRoYXQKPiArICogc3VwcG9ydHMgb25seSA4Yml0cyBwZXIgY2hhbm5lbAo+ICsgKi8KPiAr
I2RlZmluZSBNQUxJRFBfQkdORF9DT0xPUl9SCQkweDAwMAo+ICsjZGVmaW5lIE1BTElEUF9CR05E
X0NPTE9SX0cJCTB4MDAwCj4gKyNkZWZpbmUgTUFMSURQX0JHTkRfQ09MT1JfQgkJMHgwMDAKPiAr
Cj4gKyNlbmRpZiAgLyogX19NQUxJRFBfSFdfSF9fICovCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMv
Z3B1L2RybS9hcm0vbWFsaWRwX3BsYW5lcy5jIGIvZHJpdmVycy9ncHUvZHJtL2FybS9tYWxpZHBf
cGxhbmVzLmMKPiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+IGluZGV4IDAwMDAwMDAuLjY2NWFhMGUK
PiAtLS0gL2Rldi9udWxsCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2FybS9tYWxpZHBfcGxhbmVz
LmMKPiBAQCAtMCwwICsxLDMzNyBAQAo+ICsvKgo+ICsgKiAoQykgQ09QWVJJR0hUIDIwMTYgQVJN
IExpbWl0ZWQuIEFsbCByaWdodHMgcmVzZXJ2ZWQuCj4gKyAqIEF1dGhvcjogTGl2aXUgRHVkYXUg
PExpdml1LkR1ZGF1QGFybS5jb20+Cj4gKyAqCj4gKyAqIFRoaXMgcHJvZ3JhbSBpcyBmcmVlIHNv
ZnR3YXJlIGFuZCBpcyBwcm92aWRlZCB0byB5b3UgdW5kZXIgdGhlIHRlcm1zIG9mIHRoZQo+ICsg
KiBHTlUgR2VuZXJhbCBQdWJsaWMgTGljZW5zZSB2ZXJzaW9uIDIgYXMgcHVibGlzaGVkIGJ5IHRo
ZSBGcmVlIFNvZnR3YXJlCj4gKyAqIEZvdW5kYXRpb24sIGFuZCBhbnkgdXNlIGJ5IHlvdSBvZiB0
aGlzIHByb2dyYW0gaXMgc3ViamVjdCB0byB0aGUgdGVybXMKPiArICogb2Ygc3VjaCBHTlUgbGlj
ZW5jZS4KPiArICoKPiArICogQVJNIE1hbGkgRFAgcGxhbmUgbWFuaXB1bGF0aW9uIHJvdXRpbmVz
Lgo+ICsgKi8KPiArCj4gKyNpbmNsdWRlIDxkcm0vZHJtUC5oPgo+ICsjaW5jbHVkZSA8ZHJtL2Ry
bV9hdG9taWNfaGVscGVyLmg+Cj4gKyNpbmNsdWRlIDxkcm0vZHJtX2ZiX2NtYV9oZWxwZXIuaD4K
PiArI2luY2x1ZGUgPGRybS9kcm1fZ2VtX2NtYV9oZWxwZXIuaD4KPiArI2luY2x1ZGUgPGRybS9k
cm1fcGxhbmVfaGVscGVyLmg+Cj4gKwo+ICsjaW5jbHVkZSAibWFsaWRwX2h3LmgiCj4gKyNpbmNs
dWRlICJtYWxpZHBfZHJ2LmgiCj4gKwo+ICsvKiBMYXllciBzcGVjaWZpYyByZWdpc3RlciBvZmZz
ZXRzICovCj4gKyNkZWZpbmUgTUFMSURQX0xBWUVSX0ZPUk1BVAkJMHgwMDAKPiArI2RlZmluZSBN
QUxJRFBfTEFZRVJfQ09OVFJPTAkJMHgwMDQKPiArI2RlZmluZSAgIExBWUVSX0VOQUJMRQkJCSgx
IDw8IDApCj4gKyNkZWZpbmUgICBMQVlFUl9ST1RfT0ZGU0VUCQk4Cj4gKyNkZWZpbmUgICBMQVlF
Ul9IX0ZMSVAJCQkoMSA8PCAxMCkKPiArI2RlZmluZSAgIExBWUVSX1ZfRkxJUAkJCSgxIDw8IDEx
KQo+ICsjZGVmaW5lICAgTEFZRVJfUk9UX01BU0sJCSgweGYgPDwgOCkKPiArI2RlZmluZSBNQUxJ
RFBfTEFZRVJfU0laRQkJMHgwMGMKPiArI2RlZmluZSAgIExBWUVSX0hfVkFMKHgpCQkoKCh4KSAm
IDB4MWZmZikgPDwgMCkKPiArI2RlZmluZSAgIExBWUVSX1ZfVkFMKHgpCQkoKCh4KSAmIDB4MWZm
ZikgPDwgMTYpCj4gKyNkZWZpbmUgTUFMSURQX0xBWUVSX0NPTVBfU0laRQkJMHgwMTAKPiArI2Rl
ZmluZSBNQUxJRFBfTEFZRVJfT0ZGU0VUCQkweDAxNAo+ICsjZGVmaW5lIE1BTElEUF9MQVlFUl9T
VFJJREUJCTB4MDE4Cj4gKwo+ICtzdGF0aWMgdm9pZCBtYWxpZHBfZGVfcGxhbmVfZGVzdHJveShz
dHJ1Y3QgZHJtX3BsYW5lICpwbGFuZSkKPiArewo+ICsJc3RydWN0IG1hbGlkcF9wbGFuZSAqbXAg
PSB0b19tYWxpZHBfcGxhbmUocGxhbmUpOwo+ICsKPiArCWlmIChtcC0+YmFzZS5mYikKPiArCQlk
cm1fZnJhbWVidWZmZXJfdW5yZWZlcmVuY2UobXAtPmJhc2UuZmIpOwo+ICsKPiArCWRybV9wbGFu
ZV9oZWxwZXJfZGlzYWJsZShwbGFuZSk7Cj4gKwlkcm1fcGxhbmVfY2xlYW51cChwbGFuZSk7Cj4g
KwlkZXZtX2tmcmVlKHBsYW5lLT5kZXYtPmRldiwgbXApOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW50
IG1hbGlkcF9kZV9hdG9taWNfdXBkYXRlX3BsYW5lKHN0cnVjdCBkcm1fcGxhbmUgKnBsYW5lLAo+
ICsJCQkJCSBzdHJ1Y3QgZHJtX2NydGMgKmNydGMsCj4gKwkJCQkJIHN0cnVjdCBkcm1fZnJhbWVi
dWZmZXIgKmZiLAo+ICsJCQkJCSBpbnQgY3J0Y194LCBpbnQgY3J0Y195LAo+ICsJCQkJCSB1bnNp
Z25lZCBpbnQgY3J0Y193LAo+ICsJCQkJCSB1bnNpZ25lZCBpbnQgY3J0Y19oLAo+ICsJCQkJCSB1
aW50MzJfdCBzcmNfeCwgdWludDMyX3Qgc3JjX3ksCj4gKwkJCQkJIHVpbnQzMl90IHNyY193LCB1
aW50MzJfdCBzcmNfaCkKPiArewo+ICsJcmV0dXJuIGRybV9hdG9taWNfaGVscGVyX3VwZGF0ZV9w
bGFuZShwbGFuZSwgY3J0YywgZmIsIGNydGNfeCwgY3J0Y195LAo+ICsJCQkJCSAgICAgIGNydGNf
dywgY3J0Y19oLCBzcmNfeCwgc3JjX3ksCj4gKwkJCQkJICAgICAgc3JjX3csIHNyY19oKTsKPiAr
fQo+ICsKPiArc3RhdGljIGludCBtYWxpZHBfZGVfcGxhbmVfYXRvbWljX3NldF9wcm9wZXJ0eShz
dHJ1Y3QgZHJtX3BsYW5lICpwbGFuZSwKPiArCQkJCQkgICAgICAgc3RydWN0IGRybV9wbGFuZV9z
dGF0ZSAqc3RhdGUsCj4gKwkJCQkJICAgICAgIHN0cnVjdCBkcm1fcHJvcGVydHkgKnByb3BlcnR5
LAo+ICsJCQkJCSAgICAgICB1aW50NjRfdCB2YWwpCj4gK3sKPiArCXJldHVybiBkcm1fYXRvbWlj
X2hlbHBlcl9wbGFuZV9zZXRfcHJvcGVydHkocGxhbmUsIHByb3BlcnR5LCB2YWwpOwo+ICt9Cj4g
Kwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IGRybV9wbGFuZV9mdW5jcyBtYWxpZHBfZGVfcGxhbmVf
ZnVuY3MgPSB7Cj4gKwkudXBkYXRlX3BsYW5lID0gbWFsaWRwX2RlX2F0b21pY191cGRhdGVfcGxh
bmUsCj4gKwkuZGlzYWJsZV9wbGFuZSA9IGRybV9hdG9taWNfaGVscGVyX2Rpc2FibGVfcGxhbmUs
Cj4gKwkuZGVzdHJveSA9IG1hbGlkcF9kZV9wbGFuZV9kZXN0cm95LAo+ICsJLnJlc2V0ID0gZHJt
X2F0b21pY19oZWxwZXJfcGxhbmVfcmVzZXQsCj4gKwkuc2V0X3Byb3BlcnR5ID0gZHJtX2F0b21p
Y19oZWxwZXJfcGxhbmVfc2V0X3Byb3BlcnR5LAo+ICsJLmF0b21pY19zZXRfcHJvcGVydHkgPSBt
YWxpZHBfZGVfcGxhbmVfYXRvbWljX3NldF9wcm9wZXJ0eSwKPiArCS5hdG9taWNfZHVwbGljYXRl
X3N0YXRlID0gZHJtX2F0b21pY19oZWxwZXJfcGxhbmVfZHVwbGljYXRlX3N0YXRlLAo+ICsJLmF0
b21pY19kZXN0cm95X3N0YXRlID0gZHJtX2F0b21pY19oZWxwZXJfcGxhbmVfZGVzdHJveV9zdGF0
ZSwKPiArfTsKPiArCj4gK3N0YXRpYyBpbnQgbWFsaWRwX2RlX3BsYW5lX2NoZWNrKHN0cnVjdCBk
cm1fcGxhbmUgKnBsYW5lLAo+ICsJCQkJIHN0cnVjdCBkcm1fcGxhbmVfc3RhdGUgKnN0YXRlKQo+
ICt7Cj4gKwlzdHJ1Y3QgbWFsaWRwX3BsYW5lICptcCA9IHRvX21hbGlkcF9wbGFuZShwbGFuZSk7
Cj4gKwl1MzIgc3JjX3csIHNyY19oOwo+ICsKPiArCWlmICghc3RhdGUtPmNydGMgfHwgIXN0YXRl
LT5mYikKPiArCQlyZXR1cm4gMDsKPiArCj4gKwlzcmNfdyA9IHN0YXRlLT5zcmNfdyA+PiAxNjsK
PiArCXNyY19oID0gc3RhdGUtPnNyY19oID4+IDE2Owo+ICsKPiArCWlmICgoc3RhdGUtPmNydGNf
dyA+IG1wLT5od2Rldi0+bWF4X2xpbmVfc2l6ZSkgfHwKPiArCSAgICAoc3RhdGUtPmNydGNfaCA+
IG1wLT5od2Rldi0+bWF4X2xpbmVfc2l6ZSkgfHwKPiArCSAgICAoc3RhdGUtPmNydGNfdyA8IG1w
LT5od2Rldi0+bWluX2xpbmVfc2l6ZSkgfHwKPiArCSAgICAoc3RhdGUtPmNydGNfaCA8IG1wLT5o
d2Rldi0+bWluX2xpbmVfc2l6ZSkgfHwKPiArCSAgICAoc3RhdGUtPmNydGNfdyAhPSBzcmNfdykg
fHwgKHN0YXRlLT5jcnRjX2ggIT0gc3JjX2gpKQo+ICsJCXJldHVybiAtRUlOVkFMOwo+ICsKPiAr
CS8qIHBhY2tlZCBSR0I4ODggLyBCR1I4ODggY2FuJ3QgYmUgcm90YXRlZCBvciBmbGlwcGVkICov
Cj4gKwlpZiAoc3RhdGUtPnJvdGF0aW9uICE9IEJJVChEUk1fUk9UQVRFXzApICYmCj4gKwkgICAg
KHN0YXRlLT5mYi0+cGl4ZWxfZm9ybWF0ID09IERSTV9GT1JNQVRfUkdCODg4IHx8Cj4gKwkgICAg
IHN0YXRlLT5mYi0+cGl4ZWxfZm9ybWF0ID09IERSTV9GT1JNQVRfQkdSODg4KSkKPiArCQlyZXR1
cm4gLUVJTlZBTDsKPiArCj4gKwltcC0+cm90bWVtX3NpemUgPSAwOwo+ICsJaWYgKHN0YXRlLT5y
b3RhdGlvbiAmIE1BTElEUF9ST1RBVEVEX01BU0spIHsKPiArCQlpbnQgdmFsOwo+ICsKPiArCQl2
YWwgPSBtcC0+aHdkZXYtPnJvdG1lbV9yZXF1aXJlZChtcC0+aHdkZXYsIHN0YXRlLT5jcnRjX2gs
Cj4gKwkJCQkJCSBzdGF0ZS0+Y3J0Y193LAo+ICsJCQkJCQkgc3RhdGUtPmZiLT5waXhlbF9mb3Jt
YXQpOwo+ICsJCWlmICh2YWwgPCAwKQo+ICsJCQlyZXR1cm4gdmFsOwo+ICsKPiArCQltcC0+cm90
bWVtX3NpemUgPSB2YWw7Cj4gKwl9Cj4gKwo+ICsJcmV0dXJuIDA7Cj4gK30KPiArCj4gK3N0YXRp
YyB2b2lkIG1hbGlkcF9kZV9wbGFuZV91cGRhdGUoc3RydWN0IGRybV9wbGFuZSAqcGxhbmUsCj4g
KwkJCQkgICBzdHJ1Y3QgZHJtX3BsYW5lX3N0YXRlICpvbGRfc3RhdGUpCj4gK3sKPiArCXN0cnVj
dCBkcm1fZ2VtX2NtYV9vYmplY3QgKm9iajsKPiArCXN0cnVjdCBtYWxpZHBfcGxhbmUgKm1wOwo+
ICsJY29uc3Qgc3RydWN0IG1hbGlkcF9od19yZWdtYXAgKm1hcDsKPiArCXU4IGZvcm1hdF9pZDsK
PiArCXUxNiBwdHI7Cj4gKwl1MzIgZm9ybWF0LCBzcmNfdywgc3JjX2gsIGRlc3RfdywgZGVzdF9o
LCB2YWwgPSAwOwo+ICsJaW50IG51bV9wbGFuZXMsIGk7Cj4gKwo+ICsJbXAgPSB0b19tYWxpZHBf
cGxhbmUocGxhbmUpOwo+ICsKPiArI2lmZGVmIE1BTElEUF9FTkFCTEVfQkdORF9DT0xPUl9BU19Q
UklNQVJZX1BMQU5FCj4gKwkvKiBza2lwIHRoZSBwcmltYXJ5IHBsYW5lLCBpdCBpcyB1c2luZyB0
aGUgYmFja2dyb3VuZCBjb2xvciAqLwo+ICsJaWYgKCFtcC0+bGF5ZXIgfHwgIW1wLT5sYXllci0+
aWQpCj4gKwkJcmV0dXJuOwo+ICsjZW5kaWYKPiArCj4gKwltYXAgPSAmbXAtPmh3ZGV2LT5tYXA7
Cj4gKwlmb3JtYXQgPSBwbGFuZS0+c3RhdGUtPmZiLT5waXhlbF9mb3JtYXQ7Cj4gKwlmb3JtYXRf
aWQgPSBtYWxpZHBfaHdfZ2V0X2Zvcm1hdF9pZChtYXAsIG1wLT5sYXllci0+aWQsIGZvcm1hdCk7
Cj4gKwlpZiAoZm9ybWF0X2lkID09ICh1OCktMSkKPiArCQlyZXR1cm47Cj4gKwo+ICsJbnVtX3Bs
YW5lcyA9IGRybV9mb3JtYXRfbnVtX3BsYW5lcyhmb3JtYXQpOwo+ICsKPiArCS8qIGNvbnZlcnQg
c3JjIHZhbHVlcyBmcm9tIFExNiBmaXhlZCBwb2ludCB0byBpbnRlZ2VyICovCj4gKwlzcmNfdyA9
IHBsYW5lLT5zdGF0ZS0+c3JjX3cgPj4gMTY7Cj4gKwlzcmNfaCA9IHBsYW5lLT5zdGF0ZS0+c3Jj
X2ggPj4gMTY7Cj4gKwlpZiAocGxhbmUtPnN0YXRlLT5yb3RhdGlvbiAmIE1BTElEUF9ST1RBVEVE
X01BU0spIHsKPiArCQlkZXN0X3cgPSBwbGFuZS0+c3RhdGUtPmNydGNfaDsKPiArCQlkZXN0X2gg
PSBwbGFuZS0+c3RhdGUtPmNydGNfdzsKPiArCX0gZWxzZSB7Cj4gKwkJZGVzdF93ID0gcGxhbmUt
PnN0YXRlLT5jcnRjX3c7Cj4gKwkJZGVzdF9oID0gcGxhbmUtPnN0YXRlLT5jcnRjX2g7Cj4gKwl9
Cj4gKwo+ICsJbWFsaWRwX2h3X3dyaXRlKG1wLT5od2RldiwgZm9ybWF0X2lkLCBtcC0+bGF5ZXIt
PmJhc2UpOwo+ICsKPiArCWZvciAoaSA9IDA7IGkgPCBudW1fcGxhbmVzOyBpKyspIHsKPiArCQkv
KiBjYWxjdWxhdGUgdGhlIG9mZnNldCBmb3IgdGhlIGxheWVyJ3MgcGxhbmUgcmVnaXN0ZXJzICov
Cj4gKwkJcHRyID0gbXAtPmxheWVyLT5wdHIgKyAoaSA8PCA0KTsKPiArCj4gKwkJb2JqID0gZHJt
X2ZiX2NtYV9nZXRfZ2VtX29iaihwbGFuZS0+c3RhdGUtPmZiLCBpKTsKPiArCQltYWxpZHBfaHdf
d3JpdGUobXAtPmh3ZGV2LCBsb3dlcl8zMl9iaXRzKG9iai0+cGFkZHIpLCBwdHIpOwo+ICsJCW1h
bGlkcF9od193cml0ZShtcC0+aHdkZXYsIHVwcGVyXzMyX2JpdHMob2JqLT5wYWRkciksIHB0ciAr
IDQpOwo+ICsJCW1hbGlkcF9od193cml0ZShtcC0+aHdkZXYsIHBsYW5lLT5zdGF0ZS0+ZmItPnBp
dGNoZXNbaV0sCj4gKwkJCQltcC0+bGF5ZXItPmJhc2UgKyBNQUxJRFBfTEFZRVJfU1RSSURFKTsK
PiArCX0KPiArCj4gKwltYWxpZHBfaHdfd3JpdGUobXAtPmh3ZGV2LCBMQVlFUl9IX1ZBTChzcmNf
dykgfCBMQVlFUl9WX1ZBTChzcmNfaCksCj4gKwkJCW1wLT5sYXllci0+YmFzZSArIE1BTElEUF9M
QVlFUl9TSVpFKTsKPiArCj4gKwltYWxpZHBfaHdfd3JpdGUobXAtPmh3ZGV2LCBMQVlFUl9IX1ZB
TChkZXN0X3cpIHwgTEFZRVJfVl9WQUwoZGVzdF9oKSwKPiArCQkJbXAtPmxheWVyLT5iYXNlICsg
TUFMSURQX0xBWUVSX0NPTVBfU0laRSk7Cj4gKwo+ICsJbWFsaWRwX2h3X3dyaXRlKG1wLT5od2Rl
diwgTEFZRVJfSF9WQUwocGxhbmUtPnN0YXRlLT5jcnRjX3gpIHwKPiArCQkJTEFZRVJfVl9WQUwo
cGxhbmUtPnN0YXRlLT5jcnRjX3kpLAo+ICsJCQltcC0+bGF5ZXItPmJhc2UgKyBNQUxJRFBfTEFZ
RVJfT0ZGU0VUKTsKPiArCj4gKwkvKiBmaXJzdCBjbGVhciB0aGUgcm90YXRpb24gYml0cyBpbiB0
aGUgcmVnaXN0ZXIgKi8KPiArCW1hbGlkcF9od19jbGVhcmJpdHMobXAtPmh3ZGV2LCBMQVlFUl9S
T1RfTUFTSywKPiArCQkJICAgIG1wLT5sYXllci0+YmFzZSArIE1BTElEUF9MQVlFUl9DT05UUk9M
KTsKPiArCj4gKwkvKiBzZXR1cCB0aGUgcm90YXRpb24gYW5kIGF4aXMgZmxpcCBiaXRzICovCj4g
KwlpZiAocGxhbmUtPnN0YXRlLT5yb3RhdGlvbiAmIERSTV9ST1RBVEVfTUFTSykKPiArCQl2YWwg
PSBpbG9nMihwbGFuZS0+c3RhdGUtPnJvdGF0aW9uICYgRFJNX1JPVEFURV9NQVNLKSA8PCBMQVlF
Ul9ST1RfT0ZGU0VUOwo+ICsJaWYgKHBsYW5lLT5zdGF0ZS0+cm90YXRpb24gJiBCSVQoRFJNX1JF
RkxFQ1RfWCkpCj4gKwkJdmFsIHw9IExBWUVSX1ZfRkxJUDsKPiArCWlmIChwbGFuZS0+c3RhdGUt
PnJvdGF0aW9uICYgQklUKERSTV9SRUZMRUNUX1kpKQo+ICsJCXZhbCB8PSBMQVlFUl9IX0ZMSVA7
Cj4gKwo+ICsJLyogc2V0IHRoZSAnZW5hYmxlIGxheWVyJyBiaXQgKi8KPiArCXZhbCB8PSBMQVlF
Ul9FTkFCTEU7Cj4gKwo+ICsJbWFsaWRwX2h3X3NldGJpdHMobXAtPmh3ZGV2LCB2YWwsCj4gKwkJ
CSAgbXAtPmxheWVyLT5iYXNlICsgTUFMSURQX0xBWUVSX0NPTlRST0wpOwo+ICt9Cj4gKwo+ICtz
dGF0aWMgdm9pZCBtYWxpZHBfZGVfcGxhbmVfZGlzYWJsZShzdHJ1Y3QgZHJtX3BsYW5lICpwbGFu
ZSwKPiArCQkJCSAgICBzdHJ1Y3QgZHJtX3BsYW5lX3N0YXRlICpzdGF0ZSkKPiArewo+ICsJc3Ry
dWN0IG1hbGlkcF9wbGFuZSAqbXAgPSB0b19tYWxpZHBfcGxhbmUocGxhbmUpOwo+ICsKPiArCW1h
bGlkcF9od19jbGVhcmJpdHMobXAtPmh3ZGV2LCBMQVlFUl9FTkFCTEUsCj4gKwkJCSAgICBtcC0+
bGF5ZXItPmJhc2UgKyBNQUxJRFBfTEFZRVJfQ09OVFJPTCk7Cj4gK30KPiArCj4gK3N0YXRpYyBj
b25zdCBzdHJ1Y3QgZHJtX3BsYW5lX2hlbHBlcl9mdW5jcyBtYWxpZHBfZGVfcGxhbmVfaGVscGVy
X2Z1bmNzID0gewo+ICsJLmF0b21pY19jaGVjayA9IG1hbGlkcF9kZV9wbGFuZV9jaGVjaywKPiAr
CS5hdG9taWNfdXBkYXRlID0gbWFsaWRwX2RlX3BsYW5lX3VwZGF0ZSwKPiArCS5hdG9taWNfZGlz
YWJsZSA9IG1hbGlkcF9kZV9wbGFuZV9kaXNhYmxlLAo+ICt9Owo+ICsKPiArI2lmZGVmIE1BTElE
UF9FTkFCTEVfQkdORF9DT0xPUl9BU19QUklNQVJZX1BMQU5FCj4gK3N0YXRpYyBjb25zdCB1aW50
MzJfdCBzYWZlX21vZGVzZXRfZm9ybWF0c1tdID0gewo+ICsJRFJNX0ZPUk1BVF9YUkdCODg4OCwK
PiArCURSTV9GT1JNQVRfQVJHQjg4ODgsCj4gK307Cj4gKwo+ICtzdGF0aWMgaW50IG1hbGlkcF9k
ZV9jcmVhdGVfcHJpbWFyeV9wbGFuZShzdHJ1Y3QgZHJtX2RldmljZSAqZHJtKQo+ICt7Cj4gKwlz
dHJ1Y3QgbWFsaWRwX2RybSAqbWFsaWRwID0gZHJtLT5kZXZfcHJpdmF0ZTsKPiArCXN0cnVjdCBt
YWxpZHBfcGxhbmUgKnBsYW5lOwo+ICsJaW50IHJldDsKPiArCj4gKwlwbGFuZSA9IGRldm1fa3ph
bGxvYyhkcm0tPmRldiwgc2l6ZW9mKCpwbGFuZSksIEdGUF9LRVJORUwpOwo+ICsJaWYgKCFwbGFu
ZSkKPiArCQlyZXR1cm4gLUVOT01FTTsKPiArCj4gKwlyZXQgPSBkcm1fdW5pdmVyc2FsX3BsYW5l
X2luaXQoZHJtLCAmcGxhbmUtPmJhc2UsIDAsCj4gKwkJCQkgICAgICAgJm1hbGlkcF9kZV9wbGFu
ZV9mdW5jcywKPiArCQkJCSAgICAgICBzYWZlX21vZGVzZXRfZm9ybWF0cywKPiArCQkJCSAgICAg
ICBBUlJBWV9TSVpFKHNhZmVfbW9kZXNldF9mb3JtYXRzKSwKPiArCQkJCSAgICAgICBEUk1fUExB
TkVfVFlQRV9QUklNQVJZLCBOVUxMKTsKPiArCWlmIChyZXQpCj4gKwkJcmV0dXJuIHJldDsKPiAr
Cj4gKwlkcm1fcGxhbmVfaGVscGVyX2FkZCgmcGxhbmUtPmJhc2UsICZtYWxpZHBfZGVfcGxhbmVf
aGVscGVyX2Z1bmNzKTsKPiArCXBsYW5lLT5od2RldiA9IG1hbGlkcC0+ZGV2Owo+ICsKPiArCXJl
dHVybiAwOwo+ICt9Cj4gKyNlbmRpZgo+ICsKPiAraW50IG1hbGlkcF9kZV9wbGFuZXNfaW5pdChz
dHJ1Y3QgZHJtX2RldmljZSAqZHJtKQo+ICt7Cj4gKwlzdHJ1Y3QgbWFsaWRwX2RybSAqbWFsaWRw
ID0gZHJtLT5kZXZfcHJpdmF0ZTsKPiArCWNvbnN0IHN0cnVjdCBtYWxpZHBfaHdfcmVnbWFwICpt
YXAgPSAmbWFsaWRwLT5kZXYtPm1hcDsKPiArCXN0cnVjdCBtYWxpZHBfcGxhbmUgKnBsYW5lID0g
TlVMTDsKPiArCWVudW0gZHJtX3BsYW5lX3R5cGUgcGxhbmVfdHlwZTsKPiArCXVuc2lnbmVkIGxv
bmcgY3J0Y3MgPSAxIDw8IGRybS0+bW9kZV9jb25maWcubnVtX2NydGM7Cj4gKwl1MzIgKmZvcm1h
dHM7Cj4gKwlpbnQgcmV0LCBpLCBqLCBuOwo+ICsKPiArI2lmZGVmIE1BTElEUF9FTkFCTEVfQkdO
RF9DT0xPUl9BU19QUklNQVJZX1BMQU5FCj4gKwlyZXQgPSBtYWxpZHBfZGVfY3JlYXRlX3ByaW1h
cnlfcGxhbmUoZHJtKTsKPiArCWlmIChyZXQpCj4gKwkJcmV0dXJuIHJldDsKPiArCXBsYW5lX3R5
cGUgPSBEUk1fUExBTkVfVFlQRV9PVkVSTEFZOwo+ICsjZW5kaWYKPiArCj4gKwlmb3JtYXRzID0g
a2NhbGxvYyhtYXAtPm5faW5wdXRfZm9ybWF0cywgc2l6ZW9mKCpmb3JtYXRzKSwgR0ZQX0tFUk5F
TCk7Cj4gKwlpZiAoIWZvcm1hdHMpIHsKPiArCQlyZXQgPSAtRU5PTUVNOwo+ICsJCWdvdG8gY2xl
YW51cDsKPiArCX0KPiArCj4gKwlmb3IgKGkgPSAwOyBpIDwgbWFwLT5uX2xheWVyczsgaSsrKSB7
Cj4gKwkJdTggaWQgPSBtYXAtPmxheWVyc1tpXS5pZDsKPiArCj4gKwkJcGxhbmUgPSBkZXZtX2t6
YWxsb2MoZHJtLT5kZXYsIHNpemVvZigqcGxhbmUpLCBHRlBfS0VSTkVMKTsKPiArCQlpZiAoIXBs
YW5lKSB7Cj4gKwkJCXJldCA9IC1FTk9NRU07Cj4gKwkJCWdvdG8gY2xlYW51cDsKPiArCQl9Cj4g
Kwo+ICsJCS8qIGJ1aWxkIHRoZSBsaXN0IG9mIERSTSBzdXBwb3J0ZWQgZm9ybWF0cyBiYXNlZCBv
biB0aGUgbWFwICovCj4gKwkJZm9yIChuID0gMCwgaiA9IDA7ICBqIDwgbWFwLT5uX2lucHV0X2Zv
cm1hdHM7IGorKykgewo+ICsJCQlpZiAoKG1hcC0+aW5wdXRfZm9ybWF0c1tqXS5sYXllciAmIGlk
KSA9PSBpZCkKPiArCQkJCWZvcm1hdHNbbisrXSA9IG1hcC0+aW5wdXRfZm9ybWF0c1tqXS5mb3Jt
YXQ7Cj4gKwkJfQo+ICsKPiArI2lmbmRlZiBNQUxJRFBfRU5BQkxFX0JHTkRfQ09MT1JfQVNfUFJJ
TUFSWV9QTEFORQo+ICsJCXBsYW5lX3R5cGUgPSAoaSA9PSAwKSA/IERSTV9QTEFORV9UWVBFX1BS
SU1BUlkgOgo+ICsJCQkJCURSTV9QTEFORV9UWVBFX09WRVJMQVk7Cj4gKyNlbmRpZgo+ICsJCXJl
dCA9IGRybV91bml2ZXJzYWxfcGxhbmVfaW5pdChkcm0sICZwbGFuZS0+YmFzZSwgY3J0Y3MsCj4g
KwkJCQkJICAgICAgICZtYWxpZHBfZGVfcGxhbmVfZnVuY3MsIGZvcm1hdHMsCj4gKwkJCQkJICAg
ICAgIG4sIHBsYW5lX3R5cGUsIE5VTEwpOwo+ICsJCWlmIChyZXQgPCAwKQo+ICsJCQlnb3RvIGNs
ZWFudXA7Cj4gKwo+ICsJCWlmICghZHJtLT5tb2RlX2NvbmZpZy5yb3RhdGlvbl9wcm9wZXJ0eSkg
ewo+ICsJCQl1bnNpZ25lZCBsb25nIGZsYWdzID0gQklUKERSTV9ST1RBVEVfMCkgfAo+ICsJCQkJ
CSAgICAgIEJJVChEUk1fUk9UQVRFXzkwKSB8Cj4gKwkJCQkJICAgICAgQklUKERSTV9ST1RBVEVf
MTgwKSB8Cj4gKwkJCQkJICAgICAgQklUKERSTV9ST1RBVEVfMjcwKSB8Cj4gKwkJCQkJICAgICAg
QklUKERSTV9SRUZMRUNUX1gpIHwKPiArCQkJCQkgICAgICBCSVQoRFJNX1JFRkxFQ1RfWSk7Cj4g
KwkJCWRybS0+bW9kZV9jb25maWcucm90YXRpb25fcHJvcGVydHkgPQo+ICsJCQkJZHJtX21vZGVf
Y3JlYXRlX3JvdGF0aW9uX3Byb3BlcnR5KGRybSwgZmxhZ3MpOwo+ICsJCX0KPiArCQkvKiBTTUFS
VCBsYXllciBjYW4ndCBiZSByb3RhdGVkICovCj4gKwkJaWYgKGRybS0+bW9kZV9jb25maWcucm90
YXRpb25fcHJvcGVydHkgJiYgKGlkICE9IERFX1NNQVJUKSkKPiArCQkJZHJtX29iamVjdF9hdHRh
Y2hfcHJvcGVydHkoJnBsYW5lLT5iYXNlLmJhc2UsCj4gKwkJCQkJCSAgIGRybS0+bW9kZV9jb25m
aWcucm90YXRpb25fcHJvcGVydHksCj4gKwkJCQkJCSAgIEJJVChEUk1fUk9UQVRFXzApKTsKPiAr
Cj4gKwkJZHJtX3BsYW5lX2hlbHBlcl9hZGQoJnBsYW5lLT5iYXNlLAo+ICsJCQkJICAgICAmbWFs
aWRwX2RlX3BsYW5lX2hlbHBlcl9mdW5jcyk7Cj4gKwkJcGxhbmUtPmh3ZGV2ID0gbWFsaWRwLT5k
ZXY7Cj4gKwkJcGxhbmUtPmxheWVyID0gJm1hcC0+bGF5ZXJzW2ldOwo+ICsJfQo+ICsKPiArCWtm
cmVlKGZvcm1hdHMpOwo+ICsKPiArCXJldHVybiAwOwo+ICsKPiArY2xlYW51cDoKPiArCW1hbGlk
cF9kZV9wbGFuZXNfZGVzdHJveShkcm0pOwo+ICsJa2ZyZWUoZm9ybWF0cyk7Cj4gKwo+ICsJcmV0
dXJuIHJldDsKPiArfQo+ICsKPiArdm9pZCBtYWxpZHBfZGVfcGxhbmVzX2Rlc3Ryb3koc3RydWN0
IGRybV9kZXZpY2UgKmRybSkKPiArewo+ICsJc3RydWN0IGRybV9wbGFuZSAqcCwgKnB0Owo+ICsK
PiArCWxpc3RfZm9yX2VhY2hfZW50cnlfc2FmZShwLCBwdCwgJmRybS0+bW9kZV9jb25maWcucGxh
bmVfbGlzdCwgaGVhZCkgewo+ICsJCWRybV9wbGFuZV9jbGVhbnVwKHApOwo+ICsJfQo+ICt9Cj4g
ZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9hcm0vbWFsaWRwX3JlZ3MuaCBiL2RyaXZlcnMv
Z3B1L2RybS9hcm0vbWFsaWRwX3JlZ3MuaAo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gaW5kZXgg
MDAwMDAwMC4uNzNmZWNiMwo+IC0tLSAvZGV2L251bGwKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0v
YXJtL21hbGlkcF9yZWdzLmgKPiBAQCAtMCwwICsxLDE3MiBAQAo+ICsvKgo+ICsgKiAoQykgQ09Q
WVJJR0hUIDIwMTYgQVJNIExpbWl0ZWQuIEFsbCByaWdodHMgcmVzZXJ2ZWQuCj4gKyAqIEF1dGhv
cjogTGl2aXUgRHVkYXUgPExpdml1LkR1ZGF1QGFybS5jb20+Cj4gKyAqCj4gKyAqIFRoaXMgcHJv
Z3JhbSBpcyBmcmVlIHNvZnR3YXJlIGFuZCBpcyBwcm92aWRlZCB0byB5b3UgdW5kZXIgdGhlIHRl
cm1zIG9mIHRoZQo+ICsgKiBHTlUgR2VuZXJhbCBQdWJsaWMgTGljZW5zZSB2ZXJzaW9uIDIgYXMg
cHVibGlzaGVkIGJ5IHRoZSBGcmVlIFNvZnR3YXJlCj4gKyAqIEZvdW5kYXRpb24sIGFuZCBhbnkg
dXNlIGJ5IHlvdSBvZiB0aGlzIHByb2dyYW0gaXMgc3ViamVjdCB0byB0aGUgdGVybXMKPiArICog
b2Ygc3VjaCBHTlUgbGljZW5jZS4KPiArICoKPiArICogQVJNIE1hbGkgRFA1MDAvRFA1NTAvRFA2
NTAgcmVnaXN0ZXJzIGRlZmluaXRpb24uCj4gKyAqLwo+ICsKPiArI2lmbmRlZiBfX01BTElEUF9S
RUdTX0hfXwo+ICsjZGVmaW5lIF9fTUFMSURQX1JFR1NfSF9fCj4gKwo+ICsvKgo+ICsgKiBhYmJy
ZXZpYXRpb25zIHVzZWQ6Cj4gKyAqICAgIC0gREMgLSBkaXNwbGF5IGNvcmUgKGdlbmVyYWwgc2V0
dGluZ3MpCj4gKyAqICAgIC0gREUgLSBkaXNwbGF5IGVuZ2luZQo+ICsgKiAgICAtIFNFIC0gc2Nh
bGluZyBlbmdpbmUKPiArICovCj4gKwo+ICsvKiBpbnRlcnJ1cHQgYml0IG1hc2tzICovCj4gKyNk
ZWZpbmUgTUFMSURQX0RFX0lSUV9VTkRFUlJVTgkJCSgxIDw8IDApCj4gKwo+ICsjZGVmaW5lIE1B
TElEUDUwMF9ERV9JUlFfQVhJX0VSUgkJKDEgPDwgNCkKPiArI2RlZmluZSBNQUxJRFA1MDBfREVf
SVJRX1ZTWU5DCQkJKDEgPDwgNSkKPiArI2RlZmluZSBNQUxJRFA1MDBfREVfSVJRX1BST0dfTElO
RQkJKDEgPDwgNikKPiArI2RlZmluZSBNQUxJRFA1MDBfREVfSVJRX1NBVFVSQVRJT04JCSgxIDw8
IDcpCj4gKyNkZWZpbmUgTUFMSURQNTAwX0RFX0lSUV9DT05GX1ZBTElECQkoMSA8PCA4KQo+ICsj
ZGVmaW5lIE1BTElEUDUwMF9ERV9JUlFfQ09ORl9NT0RFCQkoMSA8PCAxMSkKPiArI2RlZmluZSBN
QUxJRFA1MDBfREVfSVJRX0NPTkZfQUNUSVZFCQkoMSA8PCAxNykKPiArI2RlZmluZSBNQUxJRFA1
MDBfREVfSVJRX1BNX0FDVElWRQkJKDEgPDwgMTgpCj4gKyNkZWZpbmUgTUFMSURQNTAwX0RFX0lS
UV9URVNUTU9ERV9BQ1RJVkUJKDEgPDwgMTkpCj4gKyNkZWZpbmUgTUFMSURQNTAwX0RFX0lSUV9G
T1JDRV9CTE5LX0FDVElWRQkoMSA8PCAyNCkKPiArI2RlZmluZSBNQUxJRFA1MDBfREVfSVJRX0FY
SV9CVVNZCQkoMSA8PCAyOCkKPiArI2RlZmluZSBNQUxJRFA1MDBfREVfSVJRX0dMT0JBTAkJCSgx
IDw8IDMxKQo+ICsjZGVmaW5lIE1BTElEUDUwMF9TRV9JUlFfQ09ORl9NT0RFCQkoMSA8PCAwKQo+
ICsjZGVmaW5lIE1BTElEUDUwMF9TRV9JUlFfQ09ORl9WQUxJRAkJKDEgPDwgNCkKPiArI2RlZmlu
ZSBNQUxJRFA1MDBfU0VfSVJRX0lOSVRfQlVTWQkJKDEgPDwgNSkKPiArI2RlZmluZSBNQUxJRFA1
MDBfU0VfSVJRX0FYSV9FUlJPUgkJKDEgPDwgOCkKPiArI2RlZmluZSBNQUxJRFA1MDBfU0VfSVJR
X09WRVJSVU4JCSgxIDw8IDkpCj4gKyNkZWZpbmUgTUFMSURQNTAwX1NFX0lSUV9QUk9HX0xJTkUx
CQkoMSA8PCAxMikKPiArI2RlZmluZSBNQUxJRFA1MDBfU0VfSVJRX1BST0dfTElORTIJCSgxIDw8
IDEzKQo+ICsjZGVmaW5lIE1BTElEUDUwMF9TRV9JUlFfQ09ORl9BQ1RJVkUJCSgxIDw8IDE3KQo+
ICsjZGVmaW5lIE1BTElEUDUwMF9TRV9JUlFfUE1fQUNUSVZFCQkoMSA8PCAxOCkKPiArI2RlZmlu
ZSBNQUxJRFA1MDBfU0VfSVJRX0FYSV9CVVNZCQkoMSA8PCAyOCkKPiArI2RlZmluZSBNQUxJRFA1
MDBfU0VfSVJRX0dMT0JBTAkJCSgxIDw8IDMxKQo+ICsKPiArI2RlZmluZSBNQUxJRFA1NTBfREVf
SVJRX1NBVFVSQVRJT04JCSgxIDw8IDgpCj4gKyNkZWZpbmUgTUFMSURQNTUwX0RFX0lSUV9WU1lO
QwkJCSgxIDw8IDEyKQo+ICsjZGVmaW5lIE1BTElEUDU1MF9ERV9JUlFfUFJPR19MSU5FCQkoMSA8
PCAxMykKPiArI2RlZmluZSBNQUxJRFA1NTBfREVfSVJRX0FYSV9FUlIJCSgxIDw8IDE2KQo+ICsj
ZGVmaW5lIE1BTElEUDU1MF9TRV9JUlFfRU9XCQkJKDEgPDwgMCkKPiArI2RlZmluZSBNQUxJRFA1
NTBfU0VfSVJRX0FYSV9FUlIJCSgxIDw8IDE2KQo+ICsjZGVmaW5lIE1BTElEUDU1MF9EQ19JUlFf
Q09ORl9WQUxJRAkJKDEgPDwgMCkKPiArI2RlZmluZSBNQUxJRFA1NTBfRENfSVJRX0NPTkZfTU9E
RQkJKDEgPDwgNCkKPiArI2RlZmluZSBNQUxJRFA1NTBfRENfSVJRX0NPTkZfQUNUSVZFCQkoMSA8
PCAxNikKPiArI2RlZmluZSBNQUxJRFA1NTBfRENfSVJRX0RFCQkJKDEgPDwgMjApCj4gKyNkZWZp
bmUgTUFMSURQNTUwX0RDX0lSUV9TRQkJCSgxIDw8IDI0KQo+ICsKPiArI2RlZmluZSBNQUxJRFA2
NTBfREVfSVJRX0RSSUZUCQkJKDEgPDwgNCkKPiArCj4gKy8qIGJpdCBtYXNrcyB0aGF0IGFyZSBj
b21tb24gYmV0d2VlbiBwcm9kdWN0cyAqLwo+ICsjZGVmaW5lICAgTUFMSURQX0NGR19WQUxJRAkJ
KDEgPDwgMCkKPiArI2RlZmluZSAgIE1BTElEUF9ESVNQX0ZVTkNfSUxBQ0VECSgxIDw8IDgpCj4g
Kwo+ICsvKiByZWdpc3RlciBvZmZzZXRzIGZvciBJUlEgbWFuYWdlbWVudCAqLwo+ICsjZGVmaW5l
IE1BTElEUF9SRUdfU1RBVFVTCQkweDAwMDAwCj4gKyNkZWZpbmUgTUFMSURQX1JFR19TRVRJUlEJ
CTB4MDAwMDQKPiArI2RlZmluZSBNQUxJRFBfUkVHX01BU0tJUlEJCTB4MDAwMDgKPiArI2RlZmlu
ZSBNQUxJRFBfUkVHX0NMRUFSSVJRCQkweDAwMDBjCj4gKwo+ICsvKiByZWdpc3RlciBvZmZzZXRz
ICovCj4gKyNkZWZpbmUgTUFMSURQX0RFX0NPUkVfSUQJCTB4MDAwMTgKPiArI2RlZmluZSBNQUxJ
RFBfREVfRElTUExBWV9GVU5DCQkweDAwMDIwCj4gKwo+ICsvKiB0aGVzZSBvZmZzZXRzIGFyZSBy
ZWxhdGl2ZSB0byBNQUxJRFA1eDBfVElNSU5HU19CQVNFICovCj4gKyNkZWZpbmUgTUFMSURQX0RF
X0hfVElNSU5HUwkJMHgwCj4gKyNkZWZpbmUgTUFMSURQX0RFX1ZfVElNSU5HUwkJMHg0Cj4gKyNk
ZWZpbmUgTUFMSURQX0RFX1NZTkNfV0lEVEgJCTB4OAo+ICsjZGVmaW5lIE1BTElEUF9ERV9IVl9B
Q1RJVkUJCTB4Ywo+ICsKPiArLyogbWFjcm9zIHRvIHNldCB2YWx1ZXMgaW50byByZWdpc3RlcnMg
Ki8KPiArI2RlZmluZSBNQUxJRFBfREVfSF9GUk9OVFBPUkNIKHgpCSgoKHgpICYgMHhmZmYpIDw8
IDApCj4gKyNkZWZpbmUgTUFMSURQX0RFX0hfQkFDS1BPUkNIKHgpCSgoKHgpICYgMHgzZmYpIDw8
IDE2KQo+ICsjZGVmaW5lIE1BTElEUDUwMF9ERV9WX0ZST05UUE9SQ0goeCkJKCgoeCkgJiAweGZm
KSA8PCAwKQo+ICsjZGVmaW5lIE1BTElEUDU1MF9ERV9WX0ZST05UUE9SQ0goeCkJKCgoeCkgJiAw
eGZmZikgPDwgMCkKPiArI2RlZmluZSBNQUxJRFBfREVfVl9CQUNLUE9SQ0goeCkJKCgoeCkgJiAw
eGZmKSA8PCAxNikKPiArI2RlZmluZSBNQUxJRFBfREVfSF9TWU5DV0lEVEgoeCkJKCgoeCkgJiAw
eDNmZikgPDwgMCkKPiArI2RlZmluZSBNQUxJRFBfREVfVl9TWU5DV0lEVEgoeCkJKCgoeCkgJiAw
eGZmKSA8PCAxNikKPiArI2RlZmluZSBNQUxJRFBfREVfSF9BQ1RJVkUoeCkJCSgoKHgpICYgMHgx
ZmZmKSA8PCAwKQo+ICsjZGVmaW5lIE1BTElEUF9ERV9WX0FDVElWRSh4KQkJKCgoeCkgJiAweDFm
ZmYpIDw8IDE2KQo+ICsKPiArLyogcmVnaXN0ZXIgb2Zmc2V0cyBhbmQgYml0cyBzcGVjaWZpYyB0
byBEUDUwMCAqLwo+ICsjZGVmaW5lIE1BTElEUDUwMF9EQ19CQVNFCQkweDAwMDAwCj4gKyNkZWZp
bmUgTUFMSURQNTAwX0RDX0NPTlRST0wJCTB4MDAwMGMKPiArI2RlZmluZSAgIE1BTElEUDUwMF9E
Q19DT05GSUdfUkVRCSgxIDw8IDE3KQo+ICsjZGVmaW5lICAgTUFMSURQNTAwX0hTWU5DUE9MCQko
MSA8PCAyMCkKPiArI2RlZmluZSAgIE1BTElEUDUwMF9WU1lOQ1BPTAkJKDEgPDwgMjEpCj4gKyNk
ZWZpbmUgICBNQUxJRFA1MDBfRENfQ0xFQVJfTUFTSwkweDMwMGZmZgo+ICsjZGVmaW5lIE1BTElE
UDUwMF9ERV9MSU5FX0NPVU5URVIJMHgwMDAxMAo+ICsjZGVmaW5lIE1BTElEUDUwMF9ERV9BWElf
Q09OVFJPTAkweDAwMDE0Cj4gKyNkZWZpbmUgTUFMSURQNTAwX0RFX1NFQ1VSRV9DVFJMCTB4MDAw
MWMKPiArI2RlZmluZSBNQUxJRFA1MDBfREVfQ0hST01BX0tFWQkJMHgwMDAyNAo+ICsjZGVmaW5l
IE1BTElEUDUwMF9USU1JTkdTX0JBU0UJCTB4MDAwMjgKPiArCj4gKyNkZWZpbmUgTUFMSURQNTAw
X0NPTkZJR18zRAkJMHgwMDAzOAo+ICsjZGVmaW5lIE1BTElEUDUwMF9CR05EX0NPTE9SCQkweDAw
MDNjCj4gKyNkZWZpbmUgTUFMSURQNTAwX09VVFBVVF9ERVBUSAkJMHgwMDA0NAo+ICsjZGVmaW5l
IE1BTElEUDUwMF9ZVVZfUkdCX0NPRUYJCTB4MDAwNDgKPiArI2RlZmluZSBNQUxJRFA1MDBfQ09M
T1JfQURKX0NPRUYJMHgwMDA3OAo+ICsjZGVmaW5lIE1BTElEUDUwMF9DT0VGX1RBQkxFX0FERFIJ
MHgwMDBhOAo+ICsjZGVmaW5lIE1BTElEUDUwMF9DT0VGX1RBQkxFX0RBVEEJMHgwMDBhYwo+ICsj
ZGVmaW5lIE1BTElEUDUwMF9ERV9MVl9CQVNFCQkweDAwMTAwCj4gKyNkZWZpbmUgTUFMSURQNTAw
X0RFX0xWX1BUUl9CQVNFCTB4MDAxMjQKPiArI2RlZmluZSBNQUxJRFA1MDBfREVfTEcxX0JBU0UJ
CTB4MDAyMDAKPiArI2RlZmluZSBNQUxJRFA1MDBfREVfTEcxX1BUUl9CQVNFCTB4MDAyMWMKPiAr
I2RlZmluZSBNQUxJRFA1MDBfREVfTEcyX0JBU0UJCTB4MDAzMDAKPiArI2RlZmluZSBNQUxJRFA1
MDBfREVfTEcyX1BUUl9CQVNFCTB4MDAzMWMKPiArI2RlZmluZSBNQUxJRFA1MDBfU0VfQkFTRQkJ
MHgwMGMwMAo+ICsjZGVmaW5lIE1BTElEUDUwMF9TRV9QVFJfQkFTRQkJMHgwMGUwYwo+ICsjZGVm
aW5lIE1BTElEUDUwMF9EQ19JUlFfQkFTRQkJMHgwMGYwMAo+ICsjZGVmaW5lIE1BTElEUDUwMF9D
T05GSUdfVkFMSUQJCTB4MDBmMDAKPiArI2RlZmluZSBNQUxJRFA1MDBfQ09ORklHX0lECQkweDAw
ZmQ0Cj4gKwo+ICsvKiByZWdpc3RlciBvZmZzZXRzIGFuZCBiaXRzIHNwZWNpZmljIHRvIERQNTUw
L0RQNjUwICovCj4gKyNkZWZpbmUgTUFMSURQNTUwX0RFX0NPTlRST0wJCTB4MDAwMTAKPiArI2Rl
ZmluZSBNQUxJRFA1NTBfREVfTElORV9DT1VOVEVSCTB4MDAwMTQKPiArI2RlZmluZSBNQUxJRFA1
NTBfREVfQVhJX0NPTlRST0wJMHgwMDAxOAo+ICsjZGVmaW5lIE1BTElEUDU1MF9ERV9RT1MJCTB4
MDAwMWMKPiArI2RlZmluZSBNQUxJRFA1NTBfVElNSU5HU19CQVNFCQkweDAwMDMwCj4gKyNkZWZp
bmUgTUFMSURQNTUwX0hTWU5DUE9MCQkoMSA8PCAxMikKPiArI2RlZmluZSBNQUxJRFA1NTBfVlNZ
TkNQT0wJCSgxIDw8IDI4KQo+ICsKPiArI2RlZmluZSBNQUxJRFA1NTBfREVfRElTUF9TSURFQkFO
RAkweDAwMDQwCj4gKyNkZWZpbmUgTUFMSURQNTUwX0RFX0JHTkRfQ09MT1IJCTB4MDAwNDQKPiAr
I2RlZmluZSBNQUxJRFA1NTBfREVfT1VUUFVUX0RFUFRICTB4MDAwNGMKPiArI2RlZmluZSBNQUxJ
RFA1NTBfREVfQ09MT1JfQ09FRgkJMHgwMDA1MAo+ICsjZGVmaW5lIE1BTElEUDU1MF9ERV9DT0VG
X1RBQkxFX0FERFIJMHgwMDA4MAo+ICsjZGVmaW5lIE1BTElEUDU1MF9ERV9DT0VGX1RBQkxFX0RB
VEEJMHgwMDA4NAo+ICsjZGVmaW5lIE1BTElEUDU1MF9ERV9MVjFfQkFTRQkJMHgwMDEwMAo+ICsj
ZGVmaW5lIE1BTElEUDU1MF9ERV9MVjFfUFRSX0JBU0UJMHgwMDEyNAo+ICsjZGVmaW5lIE1BTElE
UDU1MF9ERV9MVjJfQkFTRQkJMHgwMDIwMAo+ICsjZGVmaW5lIE1BTElEUDU1MF9ERV9MVjJfUFRS
X0JBU0UJMHgwMDIyNAo+ICsjZGVmaW5lIE1BTElEUDU1MF9ERV9MR19CQVNFCQkweDAwMzAwCj4g
KyNkZWZpbmUgTUFMSURQNTUwX0RFX0xHX1BUUl9CQVNFCTB4MDAzMWMKPiArI2RlZmluZSBNQUxJ
RFA1NTBfREVfTFNfQkFTRQkJMHgwMDQwMAo+ICsjZGVmaW5lIE1BTElEUDU1MF9ERV9MU19QVFJf
QkFTRQkweDAwNDJjCj4gKyNkZWZpbmUgTUFMSURQNTUwX0RFX1BFUkZfQkFTRQkJMHgwMDUwMAo+
ICsjZGVmaW5lIE1BTElEUDU1MF9TRV9CQVNFCQkweDA4MDAwCj4gKyNkZWZpbmUgTUFMSURQNTUw
X0RDX0JBU0UJCTB4MGMwMDAKPiArI2RlZmluZSBNQUxJRFA1NTBfRENfQ09OVFJPTAkJMHgwYzAx
MAo+ICsjZGVmaW5lICAgTUFMSURQNTUwX0RDX0NPTkZJR19SRVEJKDEgPDwgMTYpCj4gKyNkZWZp
bmUgTUFMSURQNTUwX0NPTkZJR19WQUxJRAkJMHgwYzAxNAo+ICsjZGVmaW5lIE1BTElEUDU1MF9D
T05GSUdfSUQJCTB4MGZmZDQKPiArCj4gKy8qCj4gKyAqIFN0YXJ0aW5nIHdpdGggRFA1NTAgdGhl
IHJlZ2lzdGVyIG1hcCBibG9ja3MgaGFzIGJlZW4gc3RhbmRhcmRpc2VkIHRvIHRoZQo+ICsgKiBm
b2xsb3dpbmcgbGF5b3V0Ogo+ICsgKgo+ICsgKiAgIE9mZnNldCAgICAgICAgICAgIEJsb2NrIHJl
Z2lzdGVycwo+ICsgKiAgMHgwMDAwMCAgICAgICAgICAgIERpc3BsYXkgRW5naW5lCj4gKyAqICAw
eDA4MDAwICAgICAgICAgICAgU2NhbGluZyBFbmdpbmUKPiArICogIDB4MGMwMDAgICAgICAgICAg
ICBEaXNwbGF5IENvcmUKPiArICogIDB4MTAwMDAgICAgICAgICAgICBTZWN1cmUgY29udHJvbAo+
ICsgKgo+ICsgKiBUaGUgb2xkIERQNTAwIElQIG1peGVzIHNvbWUgREMgd2l0aCB0aGUgREUgcmVn
aXN0ZXJzLCBoZW5jZSB0aGUgbmVlZAo+ICsgKiBmb3IgYSBtYXBwaW5nIHN0cnVjdHVyZS4KPiAr
ICovCj4gKwo+ICsjZW5kaWYgLyogX19NQUxJRFBfUkVHU19IX18gKi8KPiAtLSAKPiAyLjguMAo+
IAo+IF9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4gZHJp
LWRldmVsIG1haWxpbmcgbGlzdAo+IGRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKPiBo
dHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAoK
LS0gCj09PT09PT09PT09PT09PT09PT09CnwgSSB3b3VsZCBsaWtlIHRvIHwKfCBmaXggdGhlIHdv
cmxkLCAgfAp8IGJ1dCB0aGV5J3JlIG5vdCB8CnwgZ2l2aW5nIG1lIHRoZSAgIHwKIFwgc291cmNl
IGNvZGUhICAvCiAgLS0tLS0tLS0tLS0tLS0tCiAgICDCr1xfKOODhClfL8KvCl9fX19fX19fX19f
X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxp
c3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNr
dG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo=