All of lore.kernel.org
 help / color / mirror / Atom feed
From: Daniel Vetter <daniel@ffwll.ch>
To: intel-gfx@lists.freedesktop.org
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: ✗ Ro.CI.BAT: warning for series starting with [1/7] drm/i915: Enable edp psr error interrupts on hsw (rev2)
Date: Fri, 20 May 2016 09:48:12 +0200	[thread overview]
Message-ID: <20160520074812.GS27098@phenom.ffwll.local> (raw)
In-Reply-To: <20160519080133.3437.1531@emeril.freedesktop.org>

On Thu, May 19, 2016 at 08:01:33AM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [1/7] drm/i915: Enable edp psr error interrupts on hsw (rev2)
> URL   : https://patchwork.freedesktop.org/series/7357/
> State : warning
> 
> == Summary ==
> 
> Series 7357v2 Series without cover letter
> http://patchwork.freedesktop.org/api/1.0/series/7357/revisions/2/mbox
> 
> Test drv_hangman:
>         Subgroup error-state-basic:
>                 fail       -> PASS       (ro-ilk1-i5-650)
> Test kms_pipe_crc_basic:
>         Subgroup hang-read-crc-pipe-a:
>                 pass       -> DMESG-WARN (ro-ivb2-i7-3770)

This is a pretty good wtf since blanantly impossible. We have not bug for
this, but I think I've seen it in other places. I'm creating a patch to
make this code more resilient, hopefully that helps.

Definitely unrelated to PSR since ivb just plain doesn't have PSR ...
-Daniel

> 
> ro-bdw-i5-5250u  total:219  pass:181  dwarn:0   dfail:0   fail:0   skip:38 
> ro-bdw-i7-5557U  total:219  pass:206  dwarn:0   dfail:0   fail:0   skip:13 
> ro-bdw-i7-5600u  total:219  pass:187  dwarn:0   dfail:0   fail:0   skip:32 
> ro-bsw-n3050     total:219  pass:174  dwarn:0   dfail:0   fail:3   skip:42 
> ro-byt-n2820     total:218  pass:175  dwarn:0   dfail:0   fail:2   skip:41 
> ro-hsw-i3-4010u  total:218  pass:193  dwarn:0   dfail:0   fail:0   skip:25 
> ro-hsw-i7-4770r  total:219  pass:194  dwarn:0   dfail:0   fail:0   skip:25 
> ro-ilk-i7-620lm  total:219  pass:151  dwarn:0   dfail:0   fail:1   skip:67 
> ro-ilk1-i5-650   total:214  pass:152  dwarn:0   dfail:0   fail:1   skip:61 
> ro-ivb-i7-3770   total:219  pass:183  dwarn:0   dfail:0   fail:0   skip:36 
> ro-ivb2-i7-3770  total:219  pass:186  dwarn:1   dfail:0   fail:0   skip:32 
> ro-snb-i7-2620M  total:219  pass:177  dwarn:0   dfail:0   fail:1   skip:41 
> 
> Results at /archive/results/CI_IGT_test/RO_Patchwork_934/
> 
> a2499a0 drm-intel-nightly: 2016y-05m-18d-17h-17m-55s UTC integration manifest
> 7f28bec drm/i915/psr: Implement PSR2 w/a for gen9
> 3ed1f4a drm/i915/psr: Use ->get_aux_send_ctl functions
> 89aa4b8 drm/i915/psr: Order DP aux transactions correctly
> f2227a1 drm/i915/psr: Skip aux handeshake if the vbt tells us to
> 63132de drm/i915/psr: Make idle_frames sensible again
> c77bcd8 drm/i915/psr: Try to program link training times correctly
> 068aab2 drm/i915: Enable edp psr error interrupts on hsw
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

      reply	other threads:[~2016-05-20  7:48 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-18 16:47 [PATCH 1/7] drm/i915: Enable edp psr error interrupts on hsw Daniel Vetter
2016-05-18 16:47 ` [PATCH 2/7] drm/i915/psr: Try to program link training times correctly Daniel Vetter
2016-05-18 17:39   ` [Intel-gfx] " Ville Syrjälä
2016-05-18 17:39     ` Ville Syrjälä
2016-05-18 18:04     ` Daniel Vetter
2016-05-18 18:09       ` Ville Syrjälä
2016-05-18 18:09         ` Ville Syrjälä
2016-05-19 10:50   ` Jindal, Sonika
2016-05-20  7:33     ` Daniel Vetter
2016-05-20  7:33       ` Daniel Vetter
2016-05-18 16:47 ` [PATCH 3/7] drm/i915/psr: Make idle_frames sensible again Daniel Vetter
2016-05-18 17:46   ` Ville Syrjälä
2016-05-25 22:52     ` Rodrigo Vivi
2016-05-18 16:47 ` [PATCH 4/7] drm/i915/psr: Skip aux handeshake if the vbt tells us to Daniel Vetter
2016-05-18 17:47   ` Ville Syrjälä
2016-05-18 16:47 ` [PATCH 5/7] drm/i915/psr: Order DP aux transactions correctly Daniel Vetter
2016-05-18 17:51   ` Ville Syrjälä
2016-05-18 16:47 ` [PATCH 6/7] drm/i915/psr: Use ->get_aux_send_ctl functions Daniel Vetter
2016-05-18 18:09   ` Ville Syrjälä
2016-05-18 16:47 ` [PATCH 7/7] drm/i915/psr: Implement PSR2 w/a for skl/kbl Daniel Vetter
2016-05-18 18:22   ` Ville Syrjälä
2016-05-18 18:46     ` Daniel Vetter
2016-05-18 22:07       ` Runyan, Arthur J
2016-05-19  7:14   ` [PATCH] drm/i915/psr: Implement PSR2 w/a for gen9 Daniel Vetter
2016-05-19  8:55     ` Jindal, Sonika
2016-05-20  7:53       ` Daniel Vetter
2016-05-18 17:17 ` ✗ Ro.CI.BAT: failure for series starting with [1/7] drm/i915: Enable edp psr error interrupts on hsw Patchwork
2016-05-18 18:26 ` [PATCH 1/7] " Ville Syrjälä
2016-05-19  9:36   ` Jindal, Sonika
2016-05-19  8:01 ` ✗ Ro.CI.BAT: warning for series starting with [1/7] drm/i915: Enable edp psr error interrupts on hsw (rev2) Patchwork
2016-05-20  7:48   ` Daniel Vetter [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20160520074812.GS27098@phenom.ffwll.local \
    --to=daniel@ffwll.ch \
    --cc=daniel.vetter@ffwll.ch \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.