From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rich Felker Date: Wed, 25 May 2016 02:25:33 +0000 Subject: Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings Message-Id: <20160525022533.GO21636@brightrain.aerifal.cx> List-Id: References: <2bdca4260d5bb2b3820e4309e2ba445c4c7bfbf6.1463708766.git.dalias@libc.org> <20160523205320.GA21655@rob-hp-laptop> <20160523211342.GG21636@brightrain.aerifal.cx> <57440C45.5040105@arm.com> In-Reply-To: <57440C45.5040105-5wv7dgnIgG8@public.gmane.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Marc Zyngier Cc: Rob Herring , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sh-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Ian Campbell , Jason Cooper , Kumar Gala , Mark Rutland , Pawel Moll , Thomas Gleixner On Tue, May 24, 2016 at 09:09:41AM +0100, Marc Zyngier wrote: > On 23/05/16 22:13, Rich Felker wrote: > > On Mon, May 23, 2016 at 03:53:20PM -0500, Rob Herring wrote: > >> On Fri, May 20, 2016 at 02:53:04AM +0000, Rich Felker wrote: > >>> Signed-off-by: Rich Felker > >>> --- > >>> .../bindings/interrupt-controller/jcore,aic.txt | 28 ++++++++++++++++++++++ > >>> 1 file changed, 28 insertions(+) > >>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > >>> > >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > >>> new file mode 100644 > >>> index 0000000..dc9fde8 > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > >>> @@ -0,0 +1,28 @@ > >>> +J-Core Advanced Interrupt Controller > >>> + > >>> +Required properties: > >>> + > >>> +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic > >>> + with 8 interrupt lines with programmable priorities, or "jcore,aic2" for > >>> + the "aic2" core with 64 interrupts. > >>> + > >>> +- interrupt-controller : Identifies the node as an interrupt controller > >>> + > >>> +- #interrupt-cells : Specifies the number of cells needed to encode an > >>> + interrupt source. The value shall be 1. > >> > >> No level/edge support? Need 2 cells if so. > > > > No, all the logic is in hardware. From the software side you just need > > handle_simple_irq or equivalent. > > Not even an EOI? What I mean is that there is no ack/eoi interface. While I haven't worked directly on the relevant vhdl, my understanding is that the aic clears the pending status of an interrupt atomically with acceptance of the interrupt by the cpu. Do you have any more specific questions I can try to answer? Rich From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756020AbcEYC05 (ORCPT ); Tue, 24 May 2016 22:26:57 -0400 Received: from 216-12-86-13.cv.mvl.ntelos.net ([216.12.86.13]:58311 "EHLO brightrain.aerifal.cx" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754648AbcEYCZs (ORCPT ); Tue, 24 May 2016 22:25:48 -0400 Date: Tue, 24 May 2016 22:25:33 -0400 From: Rich Felker To: Marc Zyngier Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org, Ian Campbell , Jason Cooper , Kumar Gala , Mark Rutland , Pawel Moll , Thomas Gleixner Subject: Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings Message-ID: <20160525022533.GO21636@brightrain.aerifal.cx> References: <2bdca4260d5bb2b3820e4309e2ba445c4c7bfbf6.1463708766.git.dalias@libc.org> <20160523205320.GA21655@rob-hp-laptop> <20160523211342.GG21636@brightrain.aerifal.cx> <57440C45.5040105@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <57440C45.5040105@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 24, 2016 at 09:09:41AM +0100, Marc Zyngier wrote: > On 23/05/16 22:13, Rich Felker wrote: > > On Mon, May 23, 2016 at 03:53:20PM -0500, Rob Herring wrote: > >> On Fri, May 20, 2016 at 02:53:04AM +0000, Rich Felker wrote: > >>> Signed-off-by: Rich Felker > >>> --- > >>> .../bindings/interrupt-controller/jcore,aic.txt | 28 ++++++++++++++++++++++ > >>> 1 file changed, 28 insertions(+) > >>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > >>> > >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > >>> new file mode 100644 > >>> index 0000000..dc9fde8 > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > >>> @@ -0,0 +1,28 @@ > >>> +J-Core Advanced Interrupt Controller > >>> + > >>> +Required properties: > >>> + > >>> +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic > >>> + with 8 interrupt lines with programmable priorities, or "jcore,aic2" for > >>> + the "aic2" core with 64 interrupts. > >>> + > >>> +- interrupt-controller : Identifies the node as an interrupt controller > >>> + > >>> +- #interrupt-cells : Specifies the number of cells needed to encode an > >>> + interrupt source. The value shall be 1. > >> > >> No level/edge support? Need 2 cells if so. > > > > No, all the logic is in hardware. From the software side you just need > > handle_simple_irq or equivalent. > > Not even an EOI? What I mean is that there is no ack/eoi interface. While I haven't worked directly on the relevant vhdl, my understanding is that the aic clears the pending status of an interrupt atomically with acceptance of the interrupt by the cpu. Do you have any more specific questions I can try to answer? Rich From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rich Felker Subject: Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings Date: Tue, 24 May 2016 22:25:33 -0400 Message-ID: <20160525022533.GO21636@brightrain.aerifal.cx> References: <2bdca4260d5bb2b3820e4309e2ba445c4c7bfbf6.1463708766.git.dalias@libc.org> <20160523205320.GA21655@rob-hp-laptop> <20160523211342.GG21636@brightrain.aerifal.cx> <57440C45.5040105@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <57440C45.5040105-5wv7dgnIgG8@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Marc Zyngier Cc: Rob Herring , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sh-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Ian Campbell , Jason Cooper , Kumar Gala , Mark Rutland , Pawel Moll , Thomas Gleixner List-Id: devicetree@vger.kernel.org On Tue, May 24, 2016 at 09:09:41AM +0100, Marc Zyngier wrote: > On 23/05/16 22:13, Rich Felker wrote: > > On Mon, May 23, 2016 at 03:53:20PM -0500, Rob Herring wrote: > >> On Fri, May 20, 2016 at 02:53:04AM +0000, Rich Felker wrote: > >>> Signed-off-by: Rich Felker > >>> --- > >>> .../bindings/interrupt-controller/jcore,aic.txt | 28 ++++++++++++++++++++++ > >>> 1 file changed, 28 insertions(+) > >>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > >>> > >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > >>> new file mode 100644 > >>> index 0000000..dc9fde8 > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > >>> @@ -0,0 +1,28 @@ > >>> +J-Core Advanced Interrupt Controller > >>> + > >>> +Required properties: > >>> + > >>> +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic > >>> + with 8 interrupt lines with programmable priorities, or "jcore,aic2" for > >>> + the "aic2" core with 64 interrupts. > >>> + > >>> +- interrupt-controller : Identifies the node as an interrupt controller > >>> + > >>> +- #interrupt-cells : Specifies the number of cells needed to encode an > >>> + interrupt source. The value shall be 1. > >> > >> No level/edge support? Need 2 cells if so. > > > > No, all the logic is in hardware. From the software side you just need > > handle_simple_irq or equivalent. > > Not even an EOI? What I mean is that there is no ack/eoi interface. While I haven't worked directly on the relevant vhdl, my understanding is that the aic clears the pending status of an interrupt atomically with acceptance of the interrupt by the cpu. Do you have any more specific questions I can try to answer? Rich -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html