From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58586) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b5yGl-0006b8-S8 for qemu-devel@nongnu.org; Thu, 26 May 2016 12:36:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b5yGk-0003nv-QU for qemu-devel@nongnu.org; Thu, 26 May 2016 12:36:23 -0400 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]:34794) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b5yGk-0003ne-G8 for qemu-devel@nongnu.org; Thu, 26 May 2016 12:36:22 -0400 Received: by mail-wm0-x243.google.com with SMTP id n129so6555192wmn.1 for ; Thu, 26 May 2016 09:36:22 -0700 (PDT) From: Alvise Rigo Date: Thu, 26 May 2016 18:35:48 +0200 Message-Id: <20160526163549.3276-10-a.rigo@virtualopensystems.com> In-Reply-To: <20160526163549.3276-1-a.rigo@virtualopensystems.com> References: <20160526163549.3276-1-a.rigo@virtualopensystems.com> Subject: [Qemu-devel] [RFC 09/10] cputlb: Query tlb_flush_page_all List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: mttcg@listserver.greensocs.com, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, jani.kokkonen@huawei.com, claudio.fontana@huawei.com, tech@virtualopensystems.com, fred.konrad@greensocs.com, pbonzini@redhat.com, rth@twiddle.net, serge.fdrv@gmail.com, cota@braap.org, peter.maydell@linaro.org, Alvise Rigo Secure tlb_flush_page_all() by waiting the queried flushes to be actually completed using async_wait_run_on_cpu(); Signed-off-by: Alvise Rigo --- cputlb.c | 15 ++++++++++----- include/exec/exec-all.h | 4 ++-- target-arm/helper.c | 4 ++-- 3 files changed, 14 insertions(+), 9 deletions(-) diff --git a/cputlb.c b/cputlb.c index 77a1997..4ed0cc8 100644 --- a/cputlb.c +++ b/cputlb.c @@ -346,13 +346,18 @@ static void tlb_flush_page_async_work(CPUState *cpu, void *opaque) tlb_flush_page(cpu, GPOINTER_TO_UINT(opaque)); } -void tlb_flush_page_all(target_ulong addr) +void tlb_flush_page_all(CPUState *this_cpu, target_ulong addr) { - CPUState *cpu; + CPUState *other_cpu; - CPU_FOREACH(cpu) { - async_run_on_cpu(cpu, tlb_flush_page_async_work, - GUINT_TO_POINTER(addr)); + CPU_FOREACH(other_cpu) { + if (other_cpu != this_cpu) { + async_wait_run_on_cpu(other_cpu, this_cpu, + tlb_flush_page_async_work, + GUINT_TO_POINTER(addr)); + } else { + tlb_flush_page(current_cpu, addr); + } } } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index cb891d2..36f1b81 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -191,7 +191,7 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, uintptr_t retaddr); -void tlb_flush_page_all(target_ulong addr); +void tlb_flush_page_all(CPUState *this_cpu, target_ulong addr); #else static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) { @@ -209,7 +209,7 @@ static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, CPUState *target, static inline void tlb_flush_by_mmuidx(CPUState *cpu, CPUState *target ...) { } -static inline void tlb_flush_page_all(target_ulong addr) +static inline void tlb_flush_page_all(CPUState *this_cpu, target_ulong addr) { } #endif diff --git a/target-arm/helper.c b/target-arm/helper.c index 0187c0a..8988c8b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -554,13 +554,13 @@ static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - tlb_flush_page_all(value & TARGET_PAGE_MASK); + tlb_flush_page_all(ENV_GET_CPU(env), value & TARGET_PAGE_MASK); } static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - tlb_flush_page_all(value & TARGET_PAGE_MASK); + tlb_flush_page_all(ENV_GET_CPU(env), value & TARGET_PAGE_MASK); } static const ARMCPRegInfo cp_reginfo[] = { -- 2.8.3