From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58511) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b5yGf-0006Sg-P5 for qemu-devel@nongnu.org; Thu, 26 May 2016 12:36:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b5yGd-0003lM-NS for qemu-devel@nongnu.org; Thu, 26 May 2016 12:36:16 -0400 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:34776) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b5yGd-0003ko-HO for qemu-devel@nongnu.org; Thu, 26 May 2016 12:36:15 -0400 Received: by mail-wm0-x241.google.com with SMTP id n129so6554341wmn.1 for ; Thu, 26 May 2016 09:36:15 -0700 (PDT) From: Alvise Rigo Date: Thu, 26 May 2016 18:35:44 +0200 Message-Id: <20160526163549.3276-6-a.rigo@virtualopensystems.com> In-Reply-To: <20160526163549.3276-1-a.rigo@virtualopensystems.com> References: <20160526163549.3276-1-a.rigo@virtualopensystems.com> Subject: [Qemu-devel] [RFC 05/10] target-arm: End TB after ldrex instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: mttcg@listserver.greensocs.com, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, jani.kokkonen@huawei.com, claudio.fontana@huawei.com, tech@virtualopensystems.com, fred.konrad@greensocs.com, pbonzini@redhat.com, rth@twiddle.net, serge.fdrv@gmail.com, cota@braap.org, peter.maydell@linaro.org, Alvise Rigo A VCPU executing a ldrex instruction might query flushes to other VCPUs: in this cases, the calling VCPU uses cpu_exit to exit from the cpu loop and wait the other VCPUs to perform the flush. In order to exit from the cpu loop as soon as possible, interrupt the TB after the ldrex instruction. Signed-off-by: Alvise Rigo --- target-arm/translate-a64.c | 2 ++ target-arm/translate.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 376cb1c..2a14c14 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1875,6 +1875,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (!is_store) { s->is_ldex = true; gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair); + gen_a64_set_pc_im(s->pc); + s->is_jmp = DISAS_JUMP; } else { gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair); } diff --git a/target-arm/translate.c b/target-arm/translate.c index 0677e04..7c1cb19 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -8807,6 +8807,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) default: abort(); } + gen_set_pc_im(s, s->pc); + s->is_jmp = DISAS_JUMP; } else { rm = insn & 0xf; switch (op1) { -- 2.8.3