From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752683AbcFIPXx (ORCPT ); Thu, 9 Jun 2016 11:23:53 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:34332 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752387AbcFIPXv (ORCPT ); Thu, 9 Jun 2016 11:23:51 -0400 Date: Thu, 9 Jun 2016 17:23:47 +0200 From: Carlo Caione To: Marc Zyngier Cc: Daniel Lezcano , Thomas Gleixner , Rob Herring , Mark Rutland , Dinh Nguyen , Kevin Hilman , Duc Dang , Florian Fainelli , Ray Jui , Scott Branden , Kukjin Kim , Krzysztof Kozlowski , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Masahiro Yamada , Michal Simek , =?utf-8?B?U8O2cmVu?= Brinkmann , Tirumalesh Chalamarla , Jan Glauber , Hou Zhiqiang , Wenbin Song , Yuan Yao , Liu Gang , Mingkai Hu , Rajesh Bhagat , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, linux-samsung-soc@vger.kernel.org Subject: Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger Message-ID: <20160609152347.GA9477@mephisto> References: <1465235791-7064-1-git-send-email-marc.zyngier@arm.com> <1465235791-7064-3-git-send-email-marc.zyngier@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1465235791-7064-3-git-send-email-marc.zyngier@arm.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/06/16 18:56, Marc Zyngier wrote: > The ARM architected timer specification mandates that the interrupt > associated with each timer is level triggered (which corresponds to > the "counter >= comparator" condition). > > A number of DTs are being remarkably creative, declaring the interrupt > to be edge triggered. A quick look at the TRM for the corresponding ARM > CPUs clearly shows that this is wrong, and I've corrected those. > For non-ARM designs (and in the absence of a publicly available TRM), > I've made them active low as well, which can't be completely wrong > as the GIC cannot disinguish between level low and level high. > > The respective maintainers are of course welcome to prove me wrong. > > While I was at it, I took the liberty to fix a couple of related issue, > such as some spurious affinity bits on ThunderX, and their complete > absence on ls1043a (both of which seem to be related to copy-pasting > from other DTs). > > Signed-off-by: Marc Zyngier For meson-gxbb.dtsi: Acked-by: Carlo Caione -- Carlo Caione From mboxrd@z Thu Jan 1 00:00:00 1970 From: Carlo Caione Subject: Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger Date: Thu, 9 Jun 2016 17:23:47 +0200 Message-ID: <20160609152347.GA9477@mephisto> References: <1465235791-7064-1-git-send-email-marc.zyngier@arm.com> <1465235791-7064-3-git-send-email-marc.zyngier@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Return-path: Content-Disposition: inline In-Reply-To: <1465235791-7064-3-git-send-email-marc.zyngier@arm.com> Sender: linux-kernel-owner@vger.kernel.org To: Marc Zyngier Cc: Daniel Lezcano , Thomas Gleixner , Rob Herring , Mark Rutland , Dinh Nguyen , Kevin Hilman , Duc Dang , Florian Fainelli , Ray Jui , Scott Branden , Kukjin Kim , Krzysztof Kozlowski , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Masahiro Yamada , Michal Simek , =?utf-8?B?U8O2cmVu?= Brinkmann , Tirumalesh Chalamarla , Jan Glauber Hou Zhiqiang List-Id: linux-samsung-soc@vger.kernel.org On 06/06/16 18:56, Marc Zyngier wrote: > The ARM architected timer specification mandates that the interrupt > associated with each timer is level triggered (which corresponds to > the "counter >= comparator" condition). > > A number of DTs are being remarkably creative, declaring the interrupt > to be edge triggered. A quick look at the TRM for the corresponding ARM > CPUs clearly shows that this is wrong, and I've corrected those. > For non-ARM designs (and in the absence of a publicly available TRM), > I've made them active low as well, which can't be completely wrong > as the GIC cannot disinguish between level low and level high. > > The respective maintainers are of course welcome to prove me wrong. > > While I was at it, I took the liberty to fix a couple of related issue, > such as some spurious affinity bits on ThunderX, and their complete > absence on ls1043a (both of which seem to be related to copy-pasting > from other DTs). > > Signed-off-by: Marc Zyngier For meson-gxbb.dtsi: Acked-by: Carlo Caione -- Carlo Caione From mboxrd@z Thu Jan 1 00:00:00 1970 From: carlo@caione.org (Carlo Caione) Date: Thu, 9 Jun 2016 17:23:47 +0200 Subject: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger In-Reply-To: <1465235791-7064-3-git-send-email-marc.zyngier@arm.com> References: <1465235791-7064-1-git-send-email-marc.zyngier@arm.com> <1465235791-7064-3-git-send-email-marc.zyngier@arm.com> Message-ID: <20160609152347.GA9477@mephisto> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 06/06/16 18:56, Marc Zyngier wrote: > The ARM architected timer specification mandates that the interrupt > associated with each timer is level triggered (which corresponds to > the "counter >= comparator" condition). > > A number of DTs are being remarkably creative, declaring the interrupt > to be edge triggered. A quick look at the TRM for the corresponding ARM > CPUs clearly shows that this is wrong, and I've corrected those. > For non-ARM designs (and in the absence of a publicly available TRM), > I've made them active low as well, which can't be completely wrong > as the GIC cannot disinguish between level low and level high. > > The respective maintainers are of course welcome to prove me wrong. > > While I was at it, I took the liberty to fix a couple of related issue, > such as some spurious affinity bits on ThunderX, and their complete > absence on ls1043a (both of which seem to be related to copy-pasting > from other DTs). > > Signed-off-by: Marc Zyngier For meson-gxbb.dtsi: Acked-by: Carlo Caione -- Carlo Caione From mboxrd@z Thu Jan 1 00:00:00 1970 From: carlo@caione.org (Carlo Caione) Date: Thu, 9 Jun 2016 17:23:47 +0200 Subject: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger In-Reply-To: <1465235791-7064-3-git-send-email-marc.zyngier@arm.com> References: <1465235791-7064-1-git-send-email-marc.zyngier@arm.com> <1465235791-7064-3-git-send-email-marc.zyngier@arm.com> Message-ID: <20160609152347.GA9477@mephisto> To: linus-amlogic@lists.infradead.org List-Id: linus-amlogic.lists.infradead.org On 06/06/16 18:56, Marc Zyngier wrote: > The ARM architected timer specification mandates that the interrupt > associated with each timer is level triggered (which corresponds to > the "counter >= comparator" condition). > > A number of DTs are being remarkably creative, declaring the interrupt > to be edge triggered. A quick look at the TRM for the corresponding ARM > CPUs clearly shows that this is wrong, and I've corrected those. > For non-ARM designs (and in the absence of a publicly available TRM), > I've made them active low as well, which can't be completely wrong > as the GIC cannot disinguish between level low and level high. > > The respective maintainers are of course welcome to prove me wrong. > > While I was at it, I took the liberty to fix a couple of related issue, > such as some spurious affinity bits on ThunderX, and their complete > absence on ls1043a (both of which seem to be related to copy-pasting > from other DTs). > > Signed-off-by: Marc Zyngier For meson-gxbb.dtsi: Acked-by: Carlo Caione -- Carlo Caione