From mboxrd@z Thu Jan 1 00:00:00 1970 From: Haozhong Zhang Subject: Re: [PATCH v4 1/3] target-i386: KVM: add basic Intel LMCE support Date: Thu, 16 Jun 2016 18:34:13 +0800 Message-ID: <20160616103413.qqtdihdto545y7hb@hz-desktop> References: <20160616060621.30422-1-haozhong.zhang@intel.com> <20160616060621.30422-2-haozhong.zhang@intel.com> <91a4203b-ceaa-3a0f-2a36-b7ae5b96fc42@redhat.com> <20160616101617.klur3zluin27vyyn@hz-desktop> <50bbc1ba-dcff-7022-fe3b-56318d119ae1@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: qemu-devel@nongnu.org, Richard Henderson , Eduardo Habkost , "Michael S . Tsirkin" , Marcelo Tosatti , kvm@vger.kernel.org, Boris Petkov , Tony Luck , Andi Kleen , rkrcmar@redhat.com, Ashok Raj To: Paolo Bonzini Return-path: Received: from mga03.intel.com ([134.134.136.65]:22052 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751681AbcFPKeR (ORCPT ); Thu, 16 Jun 2016 06:34:17 -0400 Content-Disposition: inline In-Reply-To: <50bbc1ba-dcff-7022-fe3b-56318d119ae1@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: On 06/16/16 12:23, Paolo Bonzini wrote: > > > On 16/06/2016 12:16, Haozhong Zhang wrote: > > > > > > > + has_msr_mcg_ext_ctl = true; > > > > } > > > > > > > > c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0); > > > > > > Which silicon has LMCE? We may want to enable the property for some CPU > > > models. Apart from this, the patch is pretty much okay. > > > > Skylake-EX > > ... However, all virtual CPUs can use LMCE because the rendez-vous is > done in the host. Is this correct? > Yes, if it does not confuse the guest which sees LMCE available on lower end or earlier CPUs (though I think someone would feel happy). Or do we add it only to qemu64 and kvm64? Haozhong From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44910) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDUcx-0005OW-8B for qemu-devel@nongnu.org; Thu, 16 Jun 2016 06:34:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bDUcs-0002CQ-1v for qemu-devel@nongnu.org; Thu, 16 Jun 2016 06:34:22 -0400 Received: from mga03.intel.com ([134.134.136.65]:2210) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDUcr-0002BW-Rx for qemu-devel@nongnu.org; Thu, 16 Jun 2016 06:34:17 -0400 Date: Thu, 16 Jun 2016 18:34:13 +0800 From: Haozhong Zhang Message-ID: <20160616103413.qqtdihdto545y7hb@hz-desktop> References: <20160616060621.30422-1-haozhong.zhang@intel.com> <20160616060621.30422-2-haozhong.zhang@intel.com> <91a4203b-ceaa-3a0f-2a36-b7ae5b96fc42@redhat.com> <20160616101617.klur3zluin27vyyn@hz-desktop> <50bbc1ba-dcff-7022-fe3b-56318d119ae1@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <50bbc1ba-dcff-7022-fe3b-56318d119ae1@redhat.com> Subject: Re: [Qemu-devel] [PATCH v4 1/3] target-i386: KVM: add basic Intel LMCE support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: qemu-devel@nongnu.org, Richard Henderson , Eduardo Habkost , "Michael S . Tsirkin" , Marcelo Tosatti , kvm@vger.kernel.org, Boris Petkov , Tony Luck , Andi Kleen , rkrcmar@redhat.com, Ashok Raj On 06/16/16 12:23, Paolo Bonzini wrote: > > > On 16/06/2016 12:16, Haozhong Zhang wrote: > > > > > > > + has_msr_mcg_ext_ctl = true; > > > > } > > > > > > > > c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0); > > > > > > Which silicon has LMCE? We may want to enable the property for some CPU > > > models. Apart from this, the patch is pretty much okay. > > > > Skylake-EX > > ... However, all virtual CPUs can use LMCE because the rendez-vous is > done in the host. Is this correct? > Yes, if it does not confuse the guest which sees LMCE available on lower end or earlier CPUs (though I think someone would feel happy). Or do we add it only to qemu64 and kvm64? Haozhong