From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ladislav Michl Date: Fri, 17 Jun 2016 12:07:52 +0200 Subject: [U-Boot] (no subject) In-Reply-To: <20160617100013.GA19253@localhost.localdomain> References: <20160617100013.GA19253@localhost.localdomain> Message-ID: <20160617100752.GD19943@localhost.localdomain> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Use newly introduced function. As it depends on previous RFC, lets turn in into proper patch once beforementioned problems are solved --- arch/arm/cpu/armv7/omap3/spl_id_nand.c | 33 ++++++++++----------------------- 1 file changed, 10 insertions(+), 23 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/cpu/armv7/omap3/spl_id_nand.c index 26d3aa4..0bf76fe 100644 --- a/arch/arm/cpu/armv7/omap3/spl_id_nand.c +++ b/arch/arm/cpu/armv7/omap3/spl_id_nand.c @@ -18,7 +18,7 @@ #include #include -static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE; +extern const struct gpmc *gpmc_cfg; /* * Many boards will want to know the results of the NAND_CMD_READID command @@ -31,40 +31,27 @@ int identify_nand_chip(int *mfr, int *id) int loops = 1000; /* Make sure that we have setup GPMC for NAND correctly. */ - writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1); - writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2); - writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3); - writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4); - writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5); - writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6); - - /* - * Enable the config. The CS size goes in bits 11:8. We set - * bit 6 to enable the CS and the base address goes into bits 5:0. - */ - writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) | - ((NAND_BASE >> 24) & GPMC_BASEADDR_MASK), - &gpmc_config->cs[0].config7); + set_gpmc_cs0(1); sdelay(2000); /* Issue a RESET and then READID */ - writeb(NAND_CMD_RESET, &gpmc_config->cs[0].nand_cmd); - writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd); - while ((readl(&gpmc_config->cs[0].nand_dat) & NAND_STATUS_READY) - != NAND_STATUS_READY) { + writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); + writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); + while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) + != NAND_STATUS_READY) { sdelay(100); if (--loops == 0) return 1; } - writeb(NAND_CMD_READID, &gpmc_config->cs[0].nand_cmd); + writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd); /* Set the address to read to 0x0 */ - writeb(0x0, &gpmc_config->cs[0].nand_adr); + writeb(0x0, &gpmc_cfg->cs[0].nand_adr); /* Read off the manufacturer and device id. */ - *mfr = readb(&gpmc_config->cs[0].nand_dat); - *id = readb(&gpmc_config->cs[0].nand_dat); + *mfr = readb(&gpmc_cfg->cs[0].nand_dat); + *id = readb(&gpmc_cfg->cs[0].nand_dat); return 0; } -- 2.1.4