From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoffer Dall Subject: Re: issues with emulated PCI MMIO backed by host memory under KVM Date: Tue, 28 Jun 2016 12:05:33 +0200 Message-ID: <20160628100533.GL26498@cbox> References: <20160627091619.GB26498@cbox> <20160627134910.GH1113@leverpostej> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 3E5D749B2F for ; Tue, 28 Jun 2016 05:59:36 -0400 (EDT) Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id sZ0ckRYmeYXc for ; Tue, 28 Jun 2016 05:59:35 -0400 (EDT) Received: from mail-wm0-f51.google.com (mail-wm0-f51.google.com [74.125.82.51]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 4AF7149B21 for ; Tue, 28 Jun 2016 05:59:35 -0400 (EDT) Received: by mail-wm0-f51.google.com with SMTP id f126so132874772wma.1 for ; Tue, 28 Jun 2016 03:04:45 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu To: Peter Maydell Cc: Ard Biesheuvel , Marc Zyngier , Catalin Marinas , Laszlo Ersek , "kvmarm@lists.cs.columbia.edu" List-Id: kvmarm@lists.cs.columbia.edu On Mon, Jun 27, 2016 at 03:10:20PM +0100, Peter Maydell wrote: > On 27 June 2016 at 14:49, Mark Rutland wrote: > > On Mon, Jun 27, 2016 at 02:15:29PM +0100, Peter Maydell wrote: > >> I get the impression dma-coherent is the right thing to advertise > >> anyway. Do you have the documentation to hand that specifies what > >> "dma-coherent" means? The Documentation/devicetree docs in the > >> kernel tree seem to rather unhelpfully define it as "Present if > >> dma operations are coherent", which doesn't really clarify anything > >> to me... > > > > It's ill-defined today, and the precise definition is an open question. > > See replies to [1], which seems to have stalled as of [2]. > > > > My view is that for arm/arm64 this should mean the device makes accesses > > which are coherent with Inner Shareable Normal Inner-WB Outer-WB > > attributes, as this is the functional de-facto semantics today, and > > anything short of that is not well-defined or usable. > > OK, so for any emulated device in QEMU we should specify > dma-coherent by those rules. I think our only DMA devices > in the virt board are the emulated PCI devices; dma-coherent > here is a property of the pci-controller and applies to any > device on it, right? Presumably this means that if the host > pci-controller doesn't advertise itself as dma-coherent then > we cannot do any PCI passthrough of host hardware? > Someone suggested a while back to have a second PCI controller matching the host properties for this purpose... -Christoffer