From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751858AbcGNPXg (ORCPT ); Thu, 14 Jul 2016 11:23:36 -0400 Received: from mail-it0-f44.google.com ([209.85.214.44]:37130 "EHLO mail-it0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751791AbcGNPX3 (ORCPT ); Thu, 14 Jul 2016 11:23:29 -0400 Date: Thu, 14 Jul 2016 11:23:24 -0400 From: Sean Paul To: Yakir Yang Cc: Mark Yao , Inki Dae , Jingoo Han , Heiko Stuebner , Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, daniel.vetter@ffwll.ch, emil.l.velikov@gmail.com, dianders@chromium.org, dri-devel@lists.freedesktop.org, Tomasz Figa , Javier Martinez Canillas , =?iso-8859-1?Q?St=E9phane?= Marchesin , Thierry Reding , Dan Carpenter Subject: Re: [PATCH v4 3/4] drm/bridge: analogix_dp: add the PSR function support Message-ID: <20160714152324.GC13857@seanpaul0.roam.corp.google.com> References: <1468469704-12440-1-git-send-email-ykk@rock-chips.com> <1468469753-12679-1-git-send-email-ykk@rock-chips.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1468469753-12679-1-git-send-email-ykk@rock-chips.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jul 14, 2016 at 12:15:53PM +0800, Yakir Yang wrote: > The full name of PSR is Panel Self Refresh, panel device could refresh > itself with the hardware framebuffer in panel, this would make lots of > sense to save the power consumption. > > This patch have exported two symbols for platform driver to implement > the PSR function in hardware side: > - analogix_dp_active_psr() > - analogix_dp_inactive_psr() > > Signed-off-by: Yakir Yang > --- > Changes in v4: > - Downgrade the PSR version print message to debug level. (Sean) > - Return 'void' instead of 'int' in analogix_dp_enable_sink_psr(). (Sean) > - Delete the unused read dpcd operations in analogix_dp_enable_sink_psr(). (Sean) > - Delete the arbitrary usleep_range in analogix_dp_enable_psr_crc. (Sean). > - Clean up the hardcoded values in analogix_dp_send_psr_spd(). (Sean) > - Rename "active/inactive" to "enable/disable". (Sean, Dominik) > - Keep set the PSR_VID_CRC_FLUSH gate in analogix_dp_enable_psr_crc(). > > Changes in v3: > - split analogix_dp_enable_psr(), make it more clearly > analogix_dp_detect_sink_psr() > analogix_dp_enable_sink_psr() > - remove some nosie register setting comments > > Changes in v2: > - introduce in v2, splite the common Analogix DP changes out > > drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 60 ++++++++++++++++++++++ > drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 4 ++ > drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 49 ++++++++++++++++++ > drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 28 ++++++++++ > include/drm/bridge/analogix_dp.h | 3 ++ > 5 files changed, 144 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > index 32715da..1fec91a 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > @@ -97,6 +97,62 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp) > return 0; > } > > +int analogix_dp_enable_psr(struct device *dev) > +{ > + struct analogix_dp_device *dp = dev_get_drvdata(dev); > + > + if (!dp->psr_support) > + return -EINVAL; > + > + analogix_dp_send_psr_spd(dp, EDP_VSC_PSR_STATE_ACTIVE | > + EDP_VSC_PSR_CRC_VALUES_VALID); > + return 0; > +} > +EXPORT_SYMBOL_GPL(analogix_dp_enable_psr); > + > +int analogix_dp_disable_psr(struct device *dev) > +{ > + struct analogix_dp_device *dp = dev_get_drvdata(dev); > + > + if (!dp->psr_support) > + return -EINVAL; > + > + analogix_dp_send_psr_spd(dp, 0); > + return 0; > +} > +EXPORT_SYMBOL_GPL(analogix_dp_disable_psr); > + > +static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp) > +{ > + unsigned char psr_version; > + > + analogix_dp_read_byte_from_dpcd(dp, DP_PSR_SUPPORT, &psr_version); > + dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version); > + > + return (psr_version & DP_PSR_IS_SUPPORTED) ? true : false; > +} > + > +static void analogix_dp_enable_sink_psr(struct analogix_dp_device *dp) > +{ > + unsigned char psr_en; > + > + /* Disable psr function */ > + analogix_dp_read_byte_from_dpcd(dp, DP_PSR_EN_CFG, &psr_en); > + psr_en &= ~DP_PSR_ENABLE; > + analogix_dp_write_byte_to_dpcd(dp, DP_PSR_EN_CFG, psr_en); > + > + /* Main-Link transmitter remains active during PSR active states */ > + psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION; > + analogix_dp_write_byte_to_dpcd(dp, DP_PSR_EN_CFG, psr_en); > + > + /* Enable psr function */ > + psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE | > + DP_PSR_CRC_VERIFICATION; > + analogix_dp_write_byte_to_dpcd(dp, DP_PSR_EN_CFG, psr_en); > + > + analogix_dp_enable_psr_crc(dp); > +} > + > static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) > { > int i; > @@ -921,6 +977,10 @@ static void analogix_dp_commit(struct analogix_dp_device *dp) > > /* Enable video */ > analogix_dp_start_video(dp); > + > + dp->psr_support = analogix_dp_detect_sink_psr(dp); > + if (dp->psr_support) > + analogix_dp_enable_sink_psr(dp); > } > > int analogix_dp_get_modes(struct drm_connector *connector) > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h > index b456380..6ca5dde 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h > @@ -177,6 +177,7 @@ struct analogix_dp_device { > int hpd_gpio; > bool force_hpd; > unsigned char edid[EDID_BLOCK_LENGTH * 2]; > + bool psr_support; > > struct analogix_dp_plat_data *plat_data; > }; > @@ -278,4 +279,7 @@ int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); > void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); > void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); > void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); > +void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp); > +void analogix_dp_send_psr_spd(struct analogix_dp_device *dp, int db1); > + > #endif /* _ANALOGIX_DP_CORE_H */ > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > index 48030f0..26446ae 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > @@ -26,6 +26,9 @@ > #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) > #define INT_STA_MASK INT_HPD > > +static u32 psr_spd_hbx[] = { 0x00, 0x07, 0x02, 0x08 }; > +static u32 psr_spd_pbx[] = { 0x00, 0x16, 0xCE, 0x5D }; These need to be const. Can you also please add a comment explaining where you got the values from? > + > void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable) > { > u32 reg; > @@ -1322,3 +1325,49 @@ void analogix_dp_disable_scrambling(struct analogix_dp_device *dp) > reg |= SCRAMBLING_DISABLE; > writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); > } > + > +void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp) > +{ > + writel(PSR_VID_CRC_FLUSH | PSR_VID_CRC_ENABLE, > + dp->reg_base + ANALOGIX_DP_CRC_CON); > +} > + > +void analogix_dp_send_psr_spd(struct analogix_dp_device *dp, int db1) > +{ > + unsigned int val; > + unsigned int i; > + > + /* don't send info frame */ > + val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); > + val &= ~IF_EN; > + writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); > + > + /* configure single frame update mode */ > + writel(PSR_FRAME_UP_TYPE_BURST | PSR_CRC_SEL_HARDWARE, > + dp->reg_base + ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL); > + > + /* configure VSC HB0~HB3 and PB0~PB3 */ > + for (i = 0; i < 4; i++) > + writel(psr_spd_hbx[i], dp->reg_base + ANALOGIX_DP_SPD_HB + i*4); > + for (i = 0; i < 4; i++) > + writel(psr_spd_pbx[i], dp->reg_base + ANALOGIX_DP_SPD_PB + i*4); > + > + /* configure DB0 / DB1 values */ > + writel(0x0, dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB0); > + writel(db1, dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB1); > + > + /* set reuse spd inforframe */ > + val = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); > + val |= REUSE_SPD_EN; > + writel(val, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); > + > + /* mark info frame update */ > + val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); > + val = (val | IF_UP) & ~IF_EN; > + writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); > + > + /* send info frame */ > + val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); > + val |= IF_EN; > + writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); > +} > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > index cdcc6c5..fd232b2 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > @@ -22,6 +22,8 @@ > #define ANALOGIX_DP_VIDEO_CTL_8 0x3C > #define ANALOGIX_DP_VIDEO_CTL_10 0x44 > > +#define ANALOGIX_DP_SPDIF_AUDIO_CTL_0 0xD8 > + > #define ANALOGIX_DP_PLL_REG_1 0xfc > #define ANALOGIX_DP_PLL_REG_2 0x9e4 > #define ANALOGIX_DP_PLL_REG_3 0x9e8 > @@ -30,6 +32,15 @@ > > #define ANALOGIX_DP_PD 0x12c > > +#define ANALOGIX_DP_IF_TYPE 0x244 > +#define ANALOGIX_DP_IF_PKT_DB1 0x254 > +#define ANALOGIX_DP_IF_PKT_DB2 0x258 > +#define ANALOGIX_DP_SPD_HB 0x2F8 > +#define ANALOGIX_DP_SPD_PB 0x308 > +#define ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL 0x318 > +#define ANALOGIX_DP_VSC_SHADOW_DB0 0x31C > +#define ANALOGIX_DP_VSC_SHADOW_DB1 0x320 > + > #define ANALOGIX_DP_LANE_MAP 0x35C > > #define ANALOGIX_DP_ANALOG_CTL_1 0x370 > @@ -103,6 +114,8 @@ > > #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 > > +#define ANALOGIX_DP_CRC_CON 0x890 > + > /* ANALOGIX_DP_TX_SW_RESET */ > #define RESET_DP_TX (0x1 << 0) > > @@ -151,6 +164,7 @@ > #define VID_CHK_UPDATE_TYPE_SHIFT (4) > #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) > #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) > +#define REUSE_SPD_EN (0x1 << 3) > > /* ANALOGIX_DP_VIDEO_CTL_8 */ > #define VID_HRES_TH(x) (((x) & 0xf) << 4) > @@ -167,6 +181,12 @@ > #define REF_CLK_27M (0x0 << 0) > #define REF_CLK_MASK (0x1 << 0) > > +/* ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL */ > +#define PSR_FRAME_UP_TYPE_BURST (0x1 << 0) > +#define PSR_FRAME_UP_TYPE_SINGLE (0x0 << 0) > +#define PSR_CRC_SEL_HARDWARE (0x1 << 1) > +#define PSR_CRC_SEL_MANUALLY (0x0 << 1) > + > /* ANALOGIX_DP_LANE_MAP */ > #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) > #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) > @@ -376,4 +396,12 @@ > #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) > #define VIDEO_MODE_MASTER_MODE (0x0 << 0) > > +/* ANALOGIX_DP_PKT_SEND_CTL */ > +#define IF_UP (0x1 << 4) > +#define IF_EN (0x1 << 0) > + > +/* ANALOGIX_DP_CRC_CON */ > +#define PSR_VID_CRC_FLUSH (0x1 << 2) > +#define PSR_VID_CRC_ENABLE (0x1 << 0) > + > #endif /* _ANALOGIX_DP_REG_H */ > diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h > index 261b86d..9cd8838 100644 > --- a/include/drm/bridge/analogix_dp.h > +++ b/include/drm/bridge/analogix_dp.h > @@ -38,6 +38,9 @@ struct analogix_dp_plat_data { > struct drm_connector *); > }; > > +int analogix_dp_enable_psr(struct device *dev); > +int analogix_dp_disable_psr(struct device *dev); > + > int analogix_dp_resume(struct device *dev); > int analogix_dp_suspend(struct device *dev); > > -- > 1.9.1 > > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Paul Subject: Re: [PATCH v4 3/4] drm/bridge: analogix_dp: add the PSR function support Date: Thu, 14 Jul 2016 11:23:24 -0400 Message-ID: <20160714152324.GC13857@seanpaul0.roam.corp.google.com> References: <1468469704-12440-1-git-send-email-ykk@rock-chips.com> <1468469753-12679-1-git-send-email-ykk@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <1468469753-12679-1-git-send-email-ykk@rock-chips.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Yakir Yang Cc: Thierry Reding , Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org, Javier Martinez Canillas , Mark Yao , Jingoo Han , emil.l.velikov@gmail.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, daniel.vetter@ffwll.ch, =?iso-8859-1?Q?St=E9phane?= Marchesin , Tomasz Figa , Dan Carpenter List-Id: linux-samsung-soc@vger.kernel.org T24gVGh1LCBKdWwgMTQsIDIwMTYgYXQgMTI6MTU6NTNQTSArMDgwMCwgWWFraXIgWWFuZyB3cm90 ZToKPiBUaGUgZnVsbCBuYW1lIG9mIFBTUiBpcyBQYW5lbCBTZWxmIFJlZnJlc2gsIHBhbmVsIGRl dmljZSBjb3VsZCByZWZyZXNoCj4gaXRzZWxmIHdpdGggdGhlIGhhcmR3YXJlIGZyYW1lYnVmZmVy IGluIHBhbmVsLCB0aGlzIHdvdWxkIG1ha2UgbG90cyBvZgo+IHNlbnNlIHRvIHNhdmUgdGhlIHBv d2VyIGNvbnN1bXB0aW9uLgo+IAo+IFRoaXMgcGF0Y2ggaGF2ZSBleHBvcnRlZCB0d28gc3ltYm9s cyBmb3IgcGxhdGZvcm0gZHJpdmVyIHRvIGltcGxlbWVudAo+IHRoZSBQU1IgZnVuY3Rpb24gaW4g aGFyZHdhcmUgc2lkZToKPiAtIGFuYWxvZ2l4X2RwX2FjdGl2ZV9wc3IoKQo+IC0gYW5hbG9naXhf ZHBfaW5hY3RpdmVfcHNyKCkKPiAKPiBTaWduZWQtb2ZmLWJ5OiBZYWtpciBZYW5nIDx5a2tAcm9j ay1jaGlwcy5jb20+Cj4gLS0tCj4gQ2hhbmdlcyBpbiB2NDoKPiAtIERvd25ncmFkZSB0aGUgUFNS IHZlcnNpb24gcHJpbnQgbWVzc2FnZSB0byBkZWJ1ZyBsZXZlbC4gKFNlYW4pCj4gLSBSZXR1cm4g J3ZvaWQnIGluc3RlYWQgb2YgJ2ludCcgaW4gYW5hbG9naXhfZHBfZW5hYmxlX3NpbmtfcHNyKCku IChTZWFuKQo+IC0gRGVsZXRlIHRoZSB1bnVzZWQgcmVhZCBkcGNkIG9wZXJhdGlvbnMgaW4gYW5h bG9naXhfZHBfZW5hYmxlX3NpbmtfcHNyKCkuIChTZWFuKQo+IC0gRGVsZXRlIHRoZSBhcmJpdHJh cnkgdXNsZWVwX3JhbmdlIGluIGFuYWxvZ2l4X2RwX2VuYWJsZV9wc3JfY3JjLiAoU2VhbikuCj4g LSBDbGVhbiB1cCB0aGUgaGFyZGNvZGVkIHZhbHVlcyBpbiBhbmFsb2dpeF9kcF9zZW5kX3Bzcl9z cGQoKS4gKFNlYW4pCj4gLSBSZW5hbWUgImFjdGl2ZS9pbmFjdGl2ZSIgdG8gImVuYWJsZS9kaXNh YmxlIi4gKFNlYW4sIERvbWluaWspCj4gLSBLZWVwIHNldCB0aGUgUFNSX1ZJRF9DUkNfRkxVU0gg Z2F0ZSBpbiBhbmFsb2dpeF9kcF9lbmFibGVfcHNyX2NyYygpLgo+IAo+IENoYW5nZXMgaW4gdjM6 Cj4gLSBzcGxpdCBhbmFsb2dpeF9kcF9lbmFibGVfcHNyKCksIG1ha2UgaXQgbW9yZSBjbGVhcmx5 Cj4gICAgIGFuYWxvZ2l4X2RwX2RldGVjdF9zaW5rX3BzcigpCj4gICAgIGFuYWxvZ2l4X2RwX2Vu YWJsZV9zaW5rX3BzcigpCj4gLSByZW1vdmUgc29tZSBub3NpZSByZWdpc3RlciBzZXR0aW5nIGNv bW1lbnRzCj4gCj4gQ2hhbmdlcyBpbiB2MjoKPiAtIGludHJvZHVjZSBpbiB2Miwgc3BsaXRlIHRo ZSBjb21tb24gQW5hbG9naXggRFAgY2hhbmdlcyBvdXQKPiAKPiAgZHJpdmVycy9ncHUvZHJtL2Jy aWRnZS9hbmFsb2dpeC9hbmFsb2dpeF9kcF9jb3JlLmMgfCA2MCArKysrKysrKysrKysrKysrKysr KysrCj4gIGRyaXZlcnMvZ3B1L2RybS9icmlkZ2UvYW5hbG9naXgvYW5hbG9naXhfZHBfY29yZS5o IHwgIDQgKysKPiAgZHJpdmVycy9ncHUvZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFsb2dpeF9kcF9y ZWcuYyAgfCA0OSArKysrKysrKysrKysrKysrKysKPiAgZHJpdmVycy9ncHUvZHJtL2JyaWRnZS9h bmFsb2dpeC9hbmFsb2dpeF9kcF9yZWcuaCAgfCAyOCArKysrKysrKysrCj4gIGluY2x1ZGUvZHJt L2JyaWRnZS9hbmFsb2dpeF9kcC5oICAgICAgICAgICAgICAgICAgIHwgIDMgKysKPiAgNSBmaWxl cyBjaGFuZ2VkLCAxNDQgaW5zZXJ0aW9ucygrKQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dw dS9kcm0vYnJpZGdlL2FuYWxvZ2l4L2FuYWxvZ2l4X2RwX2NvcmUuYyBiL2RyaXZlcnMvZ3B1L2Ry bS9icmlkZ2UvYW5hbG9naXgvYW5hbG9naXhfZHBfY29yZS5jCj4gaW5kZXggMzI3MTVkYS4uMWZl YzkxYSAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vYnJpZGdlL2FuYWxvZ2l4L2FuYWxv Z2l4X2RwX2NvcmUuYwo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9icmlkZ2UvYW5hbG9naXgvYW5h bG9naXhfZHBfY29yZS5jCj4gQEAgLTk3LDYgKzk3LDYyIEBAIHN0YXRpYyBpbnQgYW5hbG9naXhf ZHBfZGV0ZWN0X2hwZChzdHJ1Y3QgYW5hbG9naXhfZHBfZGV2aWNlICpkcCkKPiAgCXJldHVybiAw Owo+ICB9Cj4gIAo+ICtpbnQgYW5hbG9naXhfZHBfZW5hYmxlX3BzcihzdHJ1Y3QgZGV2aWNlICpk ZXYpCj4gK3sKPiArCXN0cnVjdCBhbmFsb2dpeF9kcF9kZXZpY2UgKmRwID0gZGV2X2dldF9kcnZk YXRhKGRldik7Cj4gKwo+ICsJaWYgKCFkcC0+cHNyX3N1cHBvcnQpCj4gKwkJcmV0dXJuIC1FSU5W QUw7Cj4gKwo+ICsJYW5hbG9naXhfZHBfc2VuZF9wc3Jfc3BkKGRwLCBFRFBfVlNDX1BTUl9TVEFU RV9BQ1RJVkUgfAo+ICsJCQkJIEVEUF9WU0NfUFNSX0NSQ19WQUxVRVNfVkFMSUQpOwo+ICsJcmV0 dXJuIDA7Cj4gK30KPiArRVhQT1JUX1NZTUJPTF9HUEwoYW5hbG9naXhfZHBfZW5hYmxlX3Bzcik7 Cj4gKwo+ICtpbnQgYW5hbG9naXhfZHBfZGlzYWJsZV9wc3Ioc3RydWN0IGRldmljZSAqZGV2KQo+ ICt7Cj4gKwlzdHJ1Y3QgYW5hbG9naXhfZHBfZGV2aWNlICpkcCA9IGRldl9nZXRfZHJ2ZGF0YShk ZXYpOwo+ICsKPiArCWlmICghZHAtPnBzcl9zdXBwb3J0KQo+ICsJCXJldHVybiAtRUlOVkFMOwo+ ICsKPiArCWFuYWxvZ2l4X2RwX3NlbmRfcHNyX3NwZChkcCwgMCk7Cj4gKwlyZXR1cm4gMDsKPiAr fQo+ICtFWFBPUlRfU1lNQk9MX0dQTChhbmFsb2dpeF9kcF9kaXNhYmxlX3Bzcik7Cj4gKwo+ICtz dGF0aWMgYm9vbCBhbmFsb2dpeF9kcF9kZXRlY3Rfc2lua19wc3Ioc3RydWN0IGFuYWxvZ2l4X2Rw X2RldmljZSAqZHApCj4gK3sKPiArCXVuc2lnbmVkIGNoYXIgcHNyX3ZlcnNpb247Cj4gKwo+ICsJ YW5hbG9naXhfZHBfcmVhZF9ieXRlX2Zyb21fZHBjZChkcCwgRFBfUFNSX1NVUFBPUlQsICZwc3Jf dmVyc2lvbik7Cj4gKwlkZXZfZGJnKGRwLT5kZXYsICJQYW5lbCBQU1IgdmVyc2lvbiA6ICV4XG4i LCBwc3JfdmVyc2lvbik7Cj4gKwo+ICsJcmV0dXJuIChwc3JfdmVyc2lvbiAmIERQX1BTUl9JU19T VVBQT1JURUQpID8gdHJ1ZSA6IGZhbHNlOwo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCBhbmFsb2dp eF9kcF9lbmFibGVfc2lua19wc3Ioc3RydWN0IGFuYWxvZ2l4X2RwX2RldmljZSAqZHApCj4gK3sK PiArCXVuc2lnbmVkIGNoYXIgcHNyX2VuOwo+ICsKPiArCS8qIERpc2FibGUgcHNyIGZ1bmN0aW9u ICovCj4gKwlhbmFsb2dpeF9kcF9yZWFkX2J5dGVfZnJvbV9kcGNkKGRwLCBEUF9QU1JfRU5fQ0ZH LCAmcHNyX2VuKTsKPiArCXBzcl9lbiAmPSB+RFBfUFNSX0VOQUJMRTsKPiArCWFuYWxvZ2l4X2Rw X3dyaXRlX2J5dGVfdG9fZHBjZChkcCwgRFBfUFNSX0VOX0NGRywgcHNyX2VuKTsKPiArCj4gKwkv KiBNYWluLUxpbmsgdHJhbnNtaXR0ZXIgcmVtYWlucyBhY3RpdmUgZHVyaW5nIFBTUiBhY3RpdmUg c3RhdGVzICovCj4gKwlwc3JfZW4gPSBEUF9QU1JfTUFJTl9MSU5LX0FDVElWRSB8IERQX1BTUl9D UkNfVkVSSUZJQ0FUSU9OOwo+ICsJYW5hbG9naXhfZHBfd3JpdGVfYnl0ZV90b19kcGNkKGRwLCBE UF9QU1JfRU5fQ0ZHLCBwc3JfZW4pOwo+ICsKPiArCS8qIEVuYWJsZSBwc3IgZnVuY3Rpb24gKi8K PiArCXBzcl9lbiA9IERQX1BTUl9FTkFCTEUgfCBEUF9QU1JfTUFJTl9MSU5LX0FDVElWRSB8Cj4g KwkJIERQX1BTUl9DUkNfVkVSSUZJQ0FUSU9OOwo+ICsJYW5hbG9naXhfZHBfd3JpdGVfYnl0ZV90 b19kcGNkKGRwLCBEUF9QU1JfRU5fQ0ZHLCBwc3JfZW4pOwo+ICsKPiArCWFuYWxvZ2l4X2RwX2Vu YWJsZV9wc3JfY3JjKGRwKTsKPiArfQo+ICsKPiAgc3RhdGljIHVuc2lnbmVkIGNoYXIgYW5hbG9n aXhfZHBfY2FsY19lZGlkX2NoZWNrX3N1bSh1bnNpZ25lZCBjaGFyICplZGlkX2RhdGEpCj4gIHsK PiAgCWludCBpOwo+IEBAIC05MjEsNiArOTc3LDEwIEBAIHN0YXRpYyB2b2lkIGFuYWxvZ2l4X2Rw X2NvbW1pdChzdHJ1Y3QgYW5hbG9naXhfZHBfZGV2aWNlICpkcCkKPiAgCj4gIAkvKiBFbmFibGUg dmlkZW8gKi8KPiAgCWFuYWxvZ2l4X2RwX3N0YXJ0X3ZpZGVvKGRwKTsKPiArCj4gKwlkcC0+cHNy X3N1cHBvcnQgPSBhbmFsb2dpeF9kcF9kZXRlY3Rfc2lua19wc3IoZHApOwo+ICsJaWYgKGRwLT5w c3Jfc3VwcG9ydCkKPiArCQlhbmFsb2dpeF9kcF9lbmFibGVfc2lua19wc3IoZHApOwo+ICB9Cj4g IAo+ICBpbnQgYW5hbG9naXhfZHBfZ2V0X21vZGVzKHN0cnVjdCBkcm1fY29ubmVjdG9yICpjb25u ZWN0b3IpCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9icmlkZ2UvYW5hbG9naXgvYW5h bG9naXhfZHBfY29yZS5oIGIvZHJpdmVycy9ncHUvZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFsb2dp eF9kcF9jb3JlLmgKPiBpbmRleCBiNDU2MzgwLi42Y2E1ZGRlIDEwMDY0NAo+IC0tLSBhL2RyaXZl cnMvZ3B1L2RybS9icmlkZ2UvYW5hbG9naXgvYW5hbG9naXhfZHBfY29yZS5oCj4gKysrIGIvZHJp dmVycy9ncHUvZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFsb2dpeF9kcF9jb3JlLmgKPiBAQCAtMTc3 LDYgKzE3Nyw3IEBAIHN0cnVjdCBhbmFsb2dpeF9kcF9kZXZpY2Ugewo+ICAJaW50CQkJaHBkX2dw aW87Cj4gIAlib29sICAgICAgICAgICAgICAgICAgICBmb3JjZV9ocGQ7Cj4gIAl1bnNpZ25lZCBj aGFyICAgICAgICAgICBlZGlkW0VESURfQkxPQ0tfTEVOR1RIICogMl07Cj4gKwlib29sCQkJcHNy X3N1cHBvcnQ7Cj4gIAo+ICAJc3RydWN0IGFuYWxvZ2l4X2RwX3BsYXRfZGF0YSAqcGxhdF9kYXRh Owo+ICB9Owo+IEBAIC0yNzgsNCArMjc5LDcgQEAgaW50IGFuYWxvZ2l4X2RwX2lzX3ZpZGVvX3N0 cmVhbV9vbihzdHJ1Y3QgYW5hbG9naXhfZHBfZGV2aWNlICpkcCk7Cj4gIHZvaWQgYW5hbG9naXhf ZHBfY29uZmlnX3ZpZGVvX3NsYXZlX21vZGUoc3RydWN0IGFuYWxvZ2l4X2RwX2RldmljZSAqZHAp Owo+ICB2b2lkIGFuYWxvZ2l4X2RwX2VuYWJsZV9zY3JhbWJsaW5nKHN0cnVjdCBhbmFsb2dpeF9k cF9kZXZpY2UgKmRwKTsKPiAgdm9pZCBhbmFsb2dpeF9kcF9kaXNhYmxlX3NjcmFtYmxpbmcoc3Ry dWN0IGFuYWxvZ2l4X2RwX2RldmljZSAqZHApOwo+ICt2b2lkIGFuYWxvZ2l4X2RwX2VuYWJsZV9w c3JfY3JjKHN0cnVjdCBhbmFsb2dpeF9kcF9kZXZpY2UgKmRwKTsKPiArdm9pZCBhbmFsb2dpeF9k cF9zZW5kX3Bzcl9zcGQoc3RydWN0IGFuYWxvZ2l4X2RwX2RldmljZSAqZHAsIGludCBkYjEpOwo+ ICsKPiAgI2VuZGlmIC8qIF9BTkFMT0dJWF9EUF9DT1JFX0ggKi8KPiBkaWZmIC0tZ2l0IGEvZHJp dmVycy9ncHUvZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFsb2dpeF9kcF9yZWcuYyBiL2RyaXZlcnMv Z3B1L2RybS9icmlkZ2UvYW5hbG9naXgvYW5hbG9naXhfZHBfcmVnLmMKPiBpbmRleCA0ODAzMGYw Li4yNjQ0NmFlIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9icmlkZ2UvYW5hbG9naXgv YW5hbG9naXhfZHBfcmVnLmMKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vYnJpZGdlL2FuYWxvZ2l4 L2FuYWxvZ2l4X2RwX3JlZy5jCj4gQEAgLTI2LDYgKzI2LDkgQEAKPiAgI2RlZmluZSBDT01NT05f SU5UX01BU0tfNAkoSE9UUExVR19DSEcgfCBIUERfTE9TVCB8IFBMVUcpCj4gICNkZWZpbmUgSU5U X1NUQV9NQVNLCQlJTlRfSFBECj4gIAo+ICtzdGF0aWMgdTMyIHBzcl9zcGRfaGJ4W10gPSB7IDB4 MDAsIDB4MDcsIDB4MDIsIDB4MDggfTsKPiArc3RhdGljIHUzMiBwc3Jfc3BkX3BieFtdID0geyAw eDAwLCAweDE2LCAweENFLCAweDVEIH07CgpUaGVzZSBuZWVkIHRvIGJlIGNvbnN0LiBDYW4geW91 IGFsc28gcGxlYXNlIGFkZCBhIGNvbW1lbnQgZXhwbGFpbmluZyB3aGVyZSB5b3UKZ290IHRoZSB2 YWx1ZXMgZnJvbT8KCj4gKwo+ICB2b2lkIGFuYWxvZ2l4X2RwX2VuYWJsZV92aWRlb19tdXRlKHN0 cnVjdCBhbmFsb2dpeF9kcF9kZXZpY2UgKmRwLCBib29sIGVuYWJsZSkKPiAgewo+ICAJdTMyIHJl ZzsKPiBAQCAtMTMyMiwzICsxMzI1LDQ5IEBAIHZvaWQgYW5hbG9naXhfZHBfZGlzYWJsZV9zY3Jh bWJsaW5nKHN0cnVjdCBhbmFsb2dpeF9kcF9kZXZpY2UgKmRwKQo+ICAJcmVnIHw9IFNDUkFNQkxJ TkdfRElTQUJMRTsKPiAgCXdyaXRlbChyZWcsIGRwLT5yZWdfYmFzZSArIEFOQUxPR0lYX0RQX1RS QUlOSU5HX1BUTl9TRVQpOwo+ICB9Cj4gKwo+ICt2b2lkIGFuYWxvZ2l4X2RwX2VuYWJsZV9wc3Jf Y3JjKHN0cnVjdCBhbmFsb2dpeF9kcF9kZXZpY2UgKmRwKQo+ICt7Cj4gKwl3cml0ZWwoUFNSX1ZJ RF9DUkNfRkxVU0ggfCBQU1JfVklEX0NSQ19FTkFCTEUsCj4gKwkgICAgICAgZHAtPnJlZ19iYXNl ICsgQU5BTE9HSVhfRFBfQ1JDX0NPTik7Cj4gK30KPiArCj4gK3ZvaWQgYW5hbG9naXhfZHBfc2Vu ZF9wc3Jfc3BkKHN0cnVjdCBhbmFsb2dpeF9kcF9kZXZpY2UgKmRwLCBpbnQgZGIxKQo+ICt7Cj4g Kwl1bnNpZ25lZCBpbnQgdmFsOwo+ICsJdW5zaWduZWQgaW50IGk7Cj4gKwo+ICsJLyogZG9uJ3Qg c2VuZCBpbmZvIGZyYW1lICovCj4gKwl2YWwgPSByZWFkbChkcC0+cmVnX2Jhc2UgKyBBTkFMT0dJ WF9EUF9QS1RfU0VORF9DVEwpOwo+ICsJdmFsICY9IH5JRl9FTjsKPiArCXdyaXRlbCh2YWwsIGRw LT5yZWdfYmFzZSArIEFOQUxPR0lYX0RQX1BLVF9TRU5EX0NUTCk7Cj4gKwo+ICsJLyogY29uZmln dXJlIHNpbmdsZSBmcmFtZSB1cGRhdGUgbW9kZSAqLwo+ICsJd3JpdGVsKFBTUl9GUkFNRV9VUF9U WVBFX0JVUlNUIHwgUFNSX0NSQ19TRUxfSEFSRFdBUkUsCj4gKwkgICAgICAgZHAtPnJlZ19iYXNl ICsgQU5BTE9HSVhfRFBfUFNSX0ZSQU1FX1VQREFURV9DVFJMKTsKPiArCj4gKwkvKiBjb25maWd1 cmUgVlNDIEhCMH5IQjMgYW5kIFBCMH5QQjMgKi8KPiArCWZvciAoaSA9IDA7IGkgPCA0OyBpKysp Cj4gKwkJd3JpdGVsKHBzcl9zcGRfaGJ4W2ldLCBkcC0+cmVnX2Jhc2UgKyBBTkFMT0dJWF9EUF9T UERfSEIgKyBpKjQpOwo+ICsJZm9yIChpID0gMDsgaSA8IDQ7IGkrKykKPiArCQl3cml0ZWwocHNy X3NwZF9wYnhbaV0sIGRwLT5yZWdfYmFzZSArIEFOQUxPR0lYX0RQX1NQRF9QQiArIGkqNCk7Cj4g Kwo+ICsJLyogY29uZmlndXJlIERCMCAvIERCMSB2YWx1ZXMgKi8KPiArCXdyaXRlbCgweDAsIGRw LT5yZWdfYmFzZSArIEFOQUxPR0lYX0RQX1ZTQ19TSEFET1dfREIwKTsKPiArCXdyaXRlbChkYjEs IGRwLT5yZWdfYmFzZSArIEFOQUxPR0lYX0RQX1ZTQ19TSEFET1dfREIxKTsKPiArCj4gKwkvKiBz ZXQgcmV1c2Ugc3BkIGluZm9yZnJhbWUgKi8KPiArCXZhbCA9IHJlYWRsKGRwLT5yZWdfYmFzZSAr IEFOQUxPR0lYX0RQX1ZJREVPX0NUTF8zKTsKPiArCXZhbCB8PSBSRVVTRV9TUERfRU47Cj4gKwl3 cml0ZWwodmFsLCBkcC0+cmVnX2Jhc2UgKyBBTkFMT0dJWF9EUF9WSURFT19DVExfMyk7Cj4gKwo+ ICsJLyogbWFyayBpbmZvIGZyYW1lIHVwZGF0ZSAqLwo+ICsJdmFsID0gcmVhZGwoZHAtPnJlZ19i YXNlICsgQU5BTE9HSVhfRFBfUEtUX1NFTkRfQ1RMKTsKPiArCXZhbCA9ICh2YWwgfCBJRl9VUCkg JiB+SUZfRU47Cj4gKwl3cml0ZWwodmFsLCBkcC0+cmVnX2Jhc2UgKyBBTkFMT0dJWF9EUF9QS1Rf U0VORF9DVEwpOwo+ICsKPiArCS8qIHNlbmQgaW5mbyBmcmFtZSAqLwo+ICsJdmFsID0gcmVhZGwo ZHAtPnJlZ19iYXNlICsgQU5BTE9HSVhfRFBfUEtUX1NFTkRfQ1RMKTsKPiArCXZhbCB8PSBJRl9F TjsKPiArCXdyaXRlbCh2YWwsIGRwLT5yZWdfYmFzZSArIEFOQUxPR0lYX0RQX1BLVF9TRU5EX0NU TCk7Cj4gK30KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2JyaWRnZS9hbmFsb2dpeC9h bmFsb2dpeF9kcF9yZWcuaCBiL2RyaXZlcnMvZ3B1L2RybS9icmlkZ2UvYW5hbG9naXgvYW5hbG9n aXhfZHBfcmVnLmgKPiBpbmRleCBjZGNjNmM1Li5mZDIzMmIyIDEwMDY0NAo+IC0tLSBhL2RyaXZl cnMvZ3B1L2RybS9icmlkZ2UvYW5hbG9naXgvYW5hbG9naXhfZHBfcmVnLmgKPiArKysgYi9kcml2 ZXJzL2dwdS9kcm0vYnJpZGdlL2FuYWxvZ2l4L2FuYWxvZ2l4X2RwX3JlZy5oCj4gQEAgLTIyLDYg KzIyLDggQEAKPiAgI2RlZmluZSBBTkFMT0dJWF9EUF9WSURFT19DVExfOAkJCTB4M0MKPiAgI2Rl ZmluZSBBTkFMT0dJWF9EUF9WSURFT19DVExfMTAJCTB4NDQKPiAgCj4gKyNkZWZpbmUgQU5BTE9H SVhfRFBfU1BESUZfQVVESU9fQ1RMXzAJCTB4RDgKPiArCj4gICNkZWZpbmUgQU5BTE9HSVhfRFBf UExMX1JFR18xCQkJMHhmYwo+ICAjZGVmaW5lIEFOQUxPR0lYX0RQX1BMTF9SRUdfMgkJCTB4OWU0 Cj4gICNkZWZpbmUgQU5BTE9HSVhfRFBfUExMX1JFR18zCQkJMHg5ZTgKPiBAQCAtMzAsNiArMzIs MTUgQEAKPiAgCj4gICNkZWZpbmUgQU5BTE9HSVhfRFBfUEQJCQkJMHgxMmMKPiAgCj4gKyNkZWZp bmUgQU5BTE9HSVhfRFBfSUZfVFlQRQkJCTB4MjQ0Cj4gKyNkZWZpbmUgQU5BTE9HSVhfRFBfSUZf UEtUX0RCMQkJCTB4MjU0Cj4gKyNkZWZpbmUgQU5BTE9HSVhfRFBfSUZfUEtUX0RCMgkJCTB4MjU4 Cj4gKyNkZWZpbmUgQU5BTE9HSVhfRFBfU1BEX0hCCQkJMHgyRjgKPiArI2RlZmluZSBBTkFMT0dJ WF9EUF9TUERfUEIJCQkweDMwOAo+ICsjZGVmaW5lIEFOQUxPR0lYX0RQX1BTUl9GUkFNRV9VUERB VEVfQ1RSTAkweDMxOAo+ICsjZGVmaW5lIEFOQUxPR0lYX0RQX1ZTQ19TSEFET1dfREIwCQkweDMx Qwo+ICsjZGVmaW5lIEFOQUxPR0lYX0RQX1ZTQ19TSEFET1dfREIxCQkweDMyMAo+ICsKPiAgI2Rl ZmluZSBBTkFMT0dJWF9EUF9MQU5FX01BUAkJCTB4MzVDCj4gIAo+ICAjZGVmaW5lIEFOQUxPR0lY X0RQX0FOQUxPR19DVExfMQkJMHgzNzAKPiBAQCAtMTAzLDYgKzExNCw4IEBACj4gIAo+ICAjZGVm aW5lIEFOQUxPR0lYX0RQX1NPQ19HRU5FUkFMX0NUTAkJMHg4MDAKPiAgCj4gKyNkZWZpbmUgQU5B TE9HSVhfRFBfQ1JDX0NPTgkJCTB4ODkwCj4gKwo+ICAvKiBBTkFMT0dJWF9EUF9UWF9TV19SRVNF VCAqLwo+ICAjZGVmaW5lIFJFU0VUX0RQX1RYCQkJCSgweDEgPDwgMCkKPiAgCj4gQEAgLTE1MSw2 ICsxNjQsNyBAQAo+ICAjZGVmaW5lIFZJRF9DSEtfVVBEQVRFX1RZUEVfU0hJRlQJCSg0KQo+ICAj ZGVmaW5lIFZJRF9DSEtfVVBEQVRFX1RZUEVfMQkJCSgweDEgPDwgNCkKPiAgI2RlZmluZSBWSURf Q0hLX1VQREFURV9UWVBFXzAJCQkoMHgwIDw8IDQpCj4gKyNkZWZpbmUgUkVVU0VfU1BEX0VOCQkJ CSgweDEgPDwgMykKPiAgCj4gIC8qIEFOQUxPR0lYX0RQX1ZJREVPX0NUTF84ICovCj4gICNkZWZp bmUgVklEX0hSRVNfVEgoeCkJCQkJKCgoeCkgJiAweGYpIDw8IDQpCj4gQEAgLTE2Nyw2ICsxODEs MTIgQEAKPiAgI2RlZmluZSBSRUZfQ0xLXzI3TQkJCQkoMHgwIDw8IDApCj4gICNkZWZpbmUgUkVG X0NMS19NQVNLCQkJCSgweDEgPDwgMCkKPiAgCj4gKy8qIEFOQUxPR0lYX0RQX1BTUl9GUkFNRV9V UERBVEVfQ1RSTCAqLwo+ICsjZGVmaW5lIFBTUl9GUkFNRV9VUF9UWVBFX0JVUlNUCQkJKDB4MSA8 PCAwKQo+ICsjZGVmaW5lIFBTUl9GUkFNRV9VUF9UWVBFX1NJTkdMRQkJKDB4MCA8PCAwKQo+ICsj ZGVmaW5lIFBTUl9DUkNfU0VMX0hBUkRXQVJFCQkJKDB4MSA8PCAxKQo+ICsjZGVmaW5lIFBTUl9D UkNfU0VMX01BTlVBTExZCQkJKDB4MCA8PCAxKQo+ICsKPiAgLyogQU5BTE9HSVhfRFBfTEFORV9N QVAgKi8KPiAgI2RlZmluZSBMQU5FM19NQVBfTE9HSUNfTEFORV8wCQkJKDB4MCA8PCA2KQo+ICAj ZGVmaW5lIExBTkUzX01BUF9MT0dJQ19MQU5FXzEJCQkoMHgxIDw8IDYpCj4gQEAgLTM3Niw0ICsz OTYsMTIgQEAKPiAgI2RlZmluZSBWSURFT19NT0RFX1NMQVZFX01PREUJCQkoMHgxIDw8IDApCj4g ICNkZWZpbmUgVklERU9fTU9ERV9NQVNURVJfTU9ERQkJCSgweDAgPDwgMCkKPiAgCj4gKy8qIEFO QUxPR0lYX0RQX1BLVF9TRU5EX0NUTCAqLwo+ICsjZGVmaW5lIElGX1VQCQkJCQkoMHgxIDw8IDQp Cj4gKyNkZWZpbmUgSUZfRU4JCQkJCSgweDEgPDwgMCkKPiArCj4gKy8qIEFOQUxPR0lYX0RQX0NS Q19DT04gKi8KPiArI2RlZmluZSBQU1JfVklEX0NSQ19GTFVTSAkJCSgweDEgPDwgMikKPiArI2Rl ZmluZSBQU1JfVklEX0NSQ19FTkFCTEUJCQkoMHgxIDw8IDApCj4gKwo+ICAjZW5kaWYgLyogX0FO QUxPR0lYX0RQX1JFR19IICovCj4gZGlmZiAtLWdpdCBhL2luY2x1ZGUvZHJtL2JyaWRnZS9hbmFs b2dpeF9kcC5oIGIvaW5jbHVkZS9kcm0vYnJpZGdlL2FuYWxvZ2l4X2RwLmgKPiBpbmRleCAyNjFi ODZkLi45Y2Q4ODM4IDEwMDY0NAo+IC0tLSBhL2luY2x1ZGUvZHJtL2JyaWRnZS9hbmFsb2dpeF9k cC5oCj4gKysrIGIvaW5jbHVkZS9kcm0vYnJpZGdlL2FuYWxvZ2l4X2RwLmgKPiBAQCAtMzgsNiAr MzgsOSBAQCBzdHJ1Y3QgYW5hbG9naXhfZHBfcGxhdF9kYXRhIHsKPiAgCQkJIHN0cnVjdCBkcm1f Y29ubmVjdG9yICopOwo+ICB9Owo+ICAKPiAraW50IGFuYWxvZ2l4X2RwX2VuYWJsZV9wc3Ioc3Ry dWN0IGRldmljZSAqZGV2KTsKPiAraW50IGFuYWxvZ2l4X2RwX2Rpc2FibGVfcHNyKHN0cnVjdCBk ZXZpY2UgKmRldik7Cj4gKwo+ICBpbnQgYW5hbG9naXhfZHBfcmVzdW1lKHN0cnVjdCBkZXZpY2Ug KmRldik7Cj4gIGludCBhbmFsb2dpeF9kcF9zdXNwZW5kKHN0cnVjdCBkZXZpY2UgKmRldik7Cj4g IAo+IC0tIAo+IDEuOS4xCj4gCj4gCj4gX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX18KPiBkcmktZGV2ZWwgbWFpbGluZyBsaXN0Cj4gZHJpLWRldmVsQGxpc3Rz LmZyZWVkZXNrdG9wLm9yZwo+IGh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4v bGlzdGluZm8vZHJpLWRldmVsCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNr dG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2Ry aS1kZXZlbAo=