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From: Pranith Kumar <bobby.prani@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	"open list:ARM" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: alex.bennee@linaro.org, serge.fdrv@gmail.com, rth@twiddle.net,
	pbonzini@redhat.com
Subject: [Qemu-devel] [PATCH v4 11/14] target-arm: Generate fences in ARMv7 frontend
Date: Thu, 14 Jul 2016 16:20:23 -0400	[thread overview]
Message-ID: <20160714202026.9727-12-bobby.prani@gmail.com> (raw)
In-Reply-To: <20160714202026.9727-1-bobby.prani@gmail.com>

Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
 target-arm/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index bd5d5cb..693d4bc 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -8083,7 +8083,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
             case 4: /* dsb */
             case 5: /* dmb */
                 ARCH(7);
-                /* We don't emulate caches so these are a no-op.  */
+                tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
                 return;
             case 6: /* isb */
                 /* We need to break the TB after this insn to execute
@@ -10432,7 +10432,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                             break;
                         case 4: /* dsb */
                         case 5: /* dmb */
-                            /* These execute as NOPs.  */
+                            tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
                             break;
                         case 6: /* isb */
                             /* We need to break the TB after this insn
-- 
2.9.0

  parent reply	other threads:[~2016-07-14 20:21 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 01/14] Introduce TCGOpcode for memory barrier Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 02/14] tcg/i386: Add support for fence Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 03/14] tcg/aarch64: " Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 04/14] tcg/arm: " Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 05/14] tcg/ia64: " Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 06/14] tcg/mips: " Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 07/14] tcg/ppc: " Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 08/14] tcg/s390: " Pranith Kumar
2016-10-16  8:47   ` Stefan Hajnoczi
2016-10-16 16:17     ` Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 09/14] tcg/sparc: " Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 10/14] tcg/tci: " Pranith Kumar
2016-07-14 20:20 ` Pranith Kumar [this message]
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 12/14] target-alpha: Generate fence op Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 13/14] target-aarch64: Generate fences for aarch64 Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 14/14] target-i386: Generate fences for x86 Pranith Kumar
2016-07-23 16:08 ` [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
2016-07-23 17:34   ` Paolo Bonzini
2016-07-23 18:00     ` Pranith Kumar
2016-08-08 14:05 ` Pranith Kumar
2016-09-07 17:33 ` Richard Henderson

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