From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36457) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bPHGi-0006PM-BO for qemu-devel@nongnu.org; Mon, 18 Jul 2016 18:44:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bPHGf-0005WH-8h for qemu-devel@nongnu.org; Mon, 18 Jul 2016 18:44:08 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44186) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bPHGf-0005WD-3P for qemu-devel@nongnu.org; Mon, 18 Jul 2016 18:44:05 -0400 Date: Tue, 19 Jul 2016 01:43:59 +0300 From: "Michael S. Tsirkin" Message-ID: <20160719014359-mutt-send-email-mst@redhat.com> References: <1468881010-27229-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1468881010-27229-1-git-send-email-mst@redhat.com> Subject: [Qemu-devel] [PULL 15/55] intel_iommu: set IR bit for ECAP register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Peter Xu , Paolo Bonzini , Richard Henderson , Eduardo Habkost From: Peter Xu Enable IR in IOMMU Extended Capability register. Signed-off-by: Peter Xu Signed-off-by: Peter Xu --- hw/i386/intel_iommu_internal.h | 2 ++ hw/i386/intel_iommu.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index b648e69..5b98a11 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -176,6 +176,8 @@ /* (offset >> 4) << 8 */ #define VTD_ECAP_IRO (DMAR_IOTLB_REG_OFFSET << 4) #define VTD_ECAP_QI (1ULL << 1) +/* Interrupt Remapping support */ +#define VTD_ECAP_IR (1ULL << 3) /* CAP_REG */ /* (offset >> 4) << 24 */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 26e322a..9c7a084 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1956,6 +1956,8 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn) */ static void vtd_init(IntelIOMMUState *s) { + X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); + memset(s->csr, 0, DMAR_REG_SIZE); memset(s->wmask, 0, DMAR_REG_SIZE); memset(s->w1cmask, 0, DMAR_REG_SIZE); @@ -1977,6 +1979,10 @@ static void vtd_init(IntelIOMMUState *s) VTD_CAP_SAGAW | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS; s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO; + if (x86_iommu->intr_supported) { + s->ecap |= VTD_ECAP_IR; + } + vtd_reset_context_cache(s); vtd_reset_iotlb(s); -- MST