From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34873) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bRVk4-0002Bc-Pz for qemu-devel@nongnu.org; Sun, 24 Jul 2016 22:35:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bRVk1-0003gw-T4 for qemu-devel@nongnu.org; Sun, 24 Jul 2016 22:35:39 -0400 Date: Mon, 25 Jul 2016 11:26:19 +1000 From: David Gibson Message-ID: <20160725012619.GH24621@voom.fritz.box> References: <1469263490-19130-1-git-send-email-nikunj@linux.vnet.ibm.com> <1469263490-19130-2-git-send-email-nikunj@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="1EKig6ypoSyM7jaD" Content-Disposition: inline In-Reply-To: <1469263490-19130-2-git-send-email-nikunj@linux.vnet.ibm.com> Subject: Re: [Qemu-devel] [RFC v2 01/13] target-ppc: Introduce Power9 family List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nikunj A Dadhania Cc: qemu-ppc@nongnu.org, rth@twiddle.net, qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com --1EKig6ypoSyM7jaD Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, Jul 23, 2016 at 02:14:38PM +0530, Nikunj A Dadhania wrote: > From: "Aneesh Kumar K.V" >=20 > Signed-off-by: Aneesh Kumar K.V > [ rebased and added POWER9 alias and POWER9 SPAPR core ] > Signed-off-by: Nikunj A Dadhania I can't really review this until the series is a bit more polished and we have a better idea how the handling of the POWER9 MMU is going to work. As it stands, this sets the P9 MMU type to something that only makes sense in guest context, not host context. > --- > hw/ppc/spapr_cpu_core.c | 5 +++ > target-ppc/cpu-models.c | 5 +++ > target-ppc/cpu-models.h | 1 + > target-ppc/cpu-qom.h | 7 ++++ > target-ppc/mmu_helper.c | 3 +- > target-ppc/translate_init.c | 85 +++++++++++++++++++++++++++++++++++++++= +++++- > 6 files changed, 104 insertions(+), 2 deletions(-) >=20 > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c > index 9347f07..766c515 100644 > --- a/hw/ppc/spapr_cpu_core.c > +++ b/hw/ppc/spapr_cpu_core.c > @@ -351,6 +351,7 @@ SPAPR_CPU_CORE_INITFN(POWER7+_v2.1, POWER7plus); > SPAPR_CPU_CORE_INITFN(POWER8_v2.0, POWER8); > SPAPR_CPU_CORE_INITFN(POWER8E_v2.1, POWER8E); > SPAPR_CPU_CORE_INITFN(POWER8NVL_v1.0, POWER8NVL); > +SPAPR_CPU_CORE_INITFN(POWER9_v1.0, POWER9); > =20 > typedef struct SPAPRCoreInfo { > const char *name; > @@ -394,6 +395,10 @@ static const SPAPRCoreInfo spapr_cores[] =3D { > { .name =3D "POWER8NVL_v1.0", .initfn =3D spapr_cpu_core_POWER8NVL_i= nitfn }, > { .name =3D "POWER8NVL", .initfn =3D spapr_cpu_core_POWER8NVL_initfn= }, > =20 > + /* POWER9 and aliases */ > + { .name =3D "POWER9_v1.0", .initfn =3D spapr_cpu_core_POWER9_initfn = }, > + { .name =3D "POWER9", .initfn =3D spapr_cpu_core_POWER9_initfn }, > + > { .name =3D NULL } > }; > =20 > diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c > index 5209e63..901cf40 100644 > --- a/target-ppc/cpu-models.c > +++ b/target-ppc/cpu-models.c > @@ -1147,6 +1147,10 @@ > "POWER8NVL v1.0") > POWERPC_DEF("970_v2.2", CPU_POWERPC_970_v22, 970, > "PowerPC 970 v2.2") > + > + POWERPC_DEF("POWER9_v1.0", CPU_POWERPC_POWER9_BASE, POW= ER9, > + "POWER9 v1.0") > + > POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970, > "PowerPC 970FX v1.0 (G5)") > POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970, > @@ -1395,6 +1399,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] =3D { > { "POWER8E", "POWER8E_v2.1" }, > { "POWER8", "POWER8_v2.0" }, > { "POWER8NVL", "POWER8NVL_v1.0" }, > + { "POWER9", "POWER9_v1.0" }, > { "970", "970_v2.2" }, > { "970fx", "970fx_v3.1" }, > { "970mp", "970mp_v1.1" }, > diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h > index f21a44c..7d9e6a2 100644 > --- a/target-ppc/cpu-models.h > +++ b/target-ppc/cpu-models.h > @@ -562,6 +562,7 @@ enum { > CPU_POWERPC_POWER8_v20 =3D 0x004D0200, > CPU_POWERPC_POWER8NVL_BASE =3D 0x004C0000, > CPU_POWERPC_POWER8NVL_v10 =3D 0x004C0100, > + CPU_POWERPC_POWER9_BASE =3D 0x004E0000, > CPU_POWERPC_970_v22 =3D 0x00390202, > CPU_POWERPC_970FX_v10 =3D 0x00391100, > CPU_POWERPC_970FX_v20 =3D 0x003C0200, > diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h > index 2864105..df2fb65 100644 > --- a/target-ppc/cpu-qom.h > +++ b/target-ppc/cpu-qom.h > @@ -86,6 +86,13 @@ enum powerpc_mmu_t { > POWERPC_MMU_2_07 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG > | POWERPC_MMU_64K > | POWERPC_MMU_AMR | 0x00000004, > + /* for now , We can add radix later if needed */ > + /* POWERPC_MMU_3_00 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG > + * | POWERPC_MMU_AMR | 0x00000005, > + */ > + > + POWERPC_MMU_3_00 =3D POWERPC_MMU_64 | POWERPC_MMU_AMR | 0x0000= 0005, > + > /* Architecture 2.07 "degraded" (no 1T segments) */ > POWERPC_MMU_2_07a =3D POWERPC_MMU_64 | POWERPC_MMU_AMR > | 0x00000004, > diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c > index 3eb3cd7..dd0cf33 100644 > --- a/target-ppc/mmu_helper.c > +++ b/target-ppc/mmu_helper.c > @@ -1935,13 +1935,14 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) > case POWERPC_MMU_2_06a: > case POWERPC_MMU_2_07: > case POWERPC_MMU_2_07a: > + case POWERPC_MMU_3_00: > #endif /* defined(TARGET_PPC64) */ > env->tlb_need_flush =3D 0; > tlb_flush(CPU(cpu), 1); > break; > default: > /* XXX: TODO */ > - cpu_abort(CPU(cpu), "Unknown MMU model\n"); > + cpu_abort(CPU(cpu), "Unknown MMU model %d\n", env->mmu_model); > break; > } > } > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 7cb7842..5b100d0 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -7459,7 +7459,8 @@ enum BOOK3S_CPU_TYPE { > BOOK3S_CPU_POWER5PLUS, > BOOK3S_CPU_POWER6, > BOOK3S_CPU_POWER7, > - BOOK3S_CPU_POWER8 > + BOOK3S_CPU_POWER8, > + BOOK3S_CPU_POWER9 > }; > =20 > static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, > @@ -8241,6 +8242,7 @@ static void init_proc_book3s_64(CPUPPCState *env, i= nt version) > break; > case BOOK3S_CPU_POWER7: > case BOOK3S_CPU_POWER8: > + case BOOK3S_CPU_POWER9: > gen_spr_book3s_ids(env); > gen_spr_amr(env, version >=3D BOOK3S_CPU_POWER8); > gen_spr_book3s_purr(env); > @@ -8293,6 +8295,7 @@ static void init_proc_book3s_64(CPUPPCState *env, i= nt version) > break; > case BOOK3S_CPU_POWER7: > case BOOK3S_CPU_POWER8: > + case BOOK3S_CPU_POWER9: > default: > env->slb_nr =3D 32; > break; > @@ -8310,6 +8313,7 @@ static void init_proc_book3s_64(CPUPPCState *env, i= nt version) > ppcPOWER7_irq_init(ppc_env_get_cpu(env)); > break; > case BOOK3S_CPU_POWER8: > + case BOOK3S_CPU_POWER9: > init_excp_POWER8(env); > ppcPOWER7_irq_init(ppc_env_get_cpu(env)); > break; > @@ -8772,6 +8776,85 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) > pcc->l1_icache_size =3D 0x8000; > pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; > } > +static void init_proc_POWER9(CPUPPCState *env) > +{ > + init_proc_book3s_64(env, BOOK3S_CPU_POWER9); > +} > + > +static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) > +{ > + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) =3D=3D CPU_POWERPC_POWER9_= BASE) { > + return true; > + } > + return false; > +} > + > +POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) > +{ > + DeviceClass *dc =3D DEVICE_CLASS(oc); > + PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); > + > + dc->fw_name =3D "PowerPC,POWER9"; > + dc->desc =3D "POWER9"; > + dc->props =3D powerpc_servercpu_properties; > + pcc->pvr_match =3D ppc_pvr_match_power9; > + pcc->pcr_mask =3D PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_0= 7; > + pcc->init_proc =3D init_proc_POWER9; > + pcc->check_pow =3D check_pow_nocheck; > + pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MF= TB | > + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | > + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | > + PPC_FLOAT_FRSQRTES | > + PPC_FLOAT_STFIWX | > + PPC_FLOAT_EXT | > + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | > + PPC_MEM_SYNC | PPC_MEM_EIEIO | > + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | > + PPC_64B | PPC_64BX | PPC_ALTIVEC | > + PPC_SEGMENT_64B | PPC_SLBI | > + PPC_POPCNTB | PPC_POPCNTWD | > + PPC_CILDST; > + pcc->insns_flags2 =3D PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | > + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | > + PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | > + PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | > + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | > + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | > + PPC2_TM | PPC2_PM_ISA206; > + pcc->msr_mask =3D (1ull << MSR_SF) | > + (1ull << MSR_TM) | > + (1ull << MSR_VR) | > + (1ull << MSR_VSX) | > + (1ull << MSR_EE) | > + (1ull << MSR_PR) | > + (1ull << MSR_FP) | > + (1ull << MSR_ME) | > + (1ull << MSR_FE0) | > + (1ull << MSR_SE) | > + (1ull << MSR_DE) | > + (1ull << MSR_FE1) | > + (1ull << MSR_IR) | > + (1ull << MSR_DR) | > + (1ull << MSR_PMM) | > + (1ull << MSR_RI) | > + (1ull << MSR_LE); > + pcc->mmu_model =3D POWERPC_MMU_3_00; > +#if defined(CONFIG_SOFTMMU) > + pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; > + /* segment page size remain the same */ > + pcc->sps =3D &POWER7_POWER8_sps; > +#endif > + pcc->excp_model =3D POWERPC_EXCP_POWER8; > + pcc->bus_model =3D PPC_FLAGS_INPUT_POWER7; > + pcc->bfd_mach =3D bfd_mach_ppc64; > + pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | > + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | > + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | > + POWERPC_FLAG_VSX | POWERPC_FLAG_TM; > + pcc->l1_dcache_size =3D 0x8000; > + pcc->l1_icache_size =3D 0x8000; > + pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; > +} > =20 > #if !defined(CONFIG_USER_ONLY) > =20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --1EKig6ypoSyM7jaD Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJXlWq7AAoJEGw4ysog2bOSCu0QAI1muNgqBEzNIvECOtWNULXT HOB41vsjdHzIamhS+9B+NLdw/h0MnWUPEmqSlBKoZ+2I2i2mVlOyejMriSpRzdJS vzjPou7t74G5MbyAwL3xIowpQ3JZZHkQEGVOdQoRAeGR2UrzRbubwbAN3u9hD8qT w47L5C/Gssau440dHSOnrgxmCrqNUmCR4Js1KtxNCvDZtVB9PrKpSvHPayaXl+YO 3ewcuIPwHSBO7moWXLpKsrHFN6dgQf4KfC1V3O5k4Er6TyDeHdgpVZteo4J4O8XU dTEkk4JtTd13Z1CUCZz1i4dKu4vApixcE44AqsQIn+OujdZFfOfsGPYp8i4+fQPN OjT/JMbDOTT+chktT1xXBefWoUn2NVkOXtyPs3b36x/yv7bQiFIt83Dp76AqlrA8 sff9mrDrSecRAd54QnzY+bu7CfI4uT80we10RGJcugHf48OxIBC98L8O0tV4wKF9 SPzC52ldRbuHOTfTDwnqDYjQwdlelg9P+UxQofMi0D1o9zgmYRcB1qZ55lMv9r05 QnD4gOtVVGb1q9nsdM2xuqEsNjrvciSTxr7+YyDKJZY07CiEPY3Q9kS8C1G+3uwe G+r6NxCckk2tcWN/rcgMG7GUVFl+WvgttyDLXokEw3vHcAaumhLzy+z0kBDbvmIx 3mE/9QAhSFlPFZ0oTaLd =ZcSq -----END PGP SIGNATURE----- --1EKig6ypoSyM7jaD--