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From: Simon Guo <wei.guo.simon@gmail.com>
To: Laurent Dufour <ldufour@linux.vnet.ibm.com>
Cc: linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au,
	Anshuman Khandual <khandual@linux.vnet.ibm.com>
Subject: Re: [PATCH] ppc64: allow ptrace to set TM bits
Date: Tue, 2 Aug 2016 13:43:53 +0800	[thread overview]
Message-ID: <20160802054351.GA16975@simonLocalRHEL7.x64> (raw)
In-Reply-To: <1469785882-9892-1-git-send-email-ldufour@linux.vnet.ibm.com>

Hi Laurent,
On Fri, Jul 29, 2016 at 11:51:22AM +0200, Laurent Dufour wrote:
>  static int set_user_msr(struct task_struct *task, unsigned long msr)
>  {
> +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> +	if (!(task->thread.regs->msr & MSR_TM)) {
> +		/* If TM is not available, discard TM bits changes */
> +		msr &= ~(MSR_TM | MSR_TS_MASK);
> +	}
> +#endif

I am not sure whether following is an issue:
Per PowerISA, any exception/interrupt will disable MSR[TM] bit 
automatically and mark MSR_TS to be suspended when it is 
transactional. It is possible that MSR[TM] = 0 and MSR[MSR_TS] != 0
(suspended). 

Will set_user_msr() be able to escape from the above?
 For example, one user space application encountered 
page fault during transaction, its task->thread.regs->msr & MSR_TM == 0
and MSR[MSR_TS] == suspended.  Then it is being traced and 
set_user_msr() is invoked on it. I think it will be incorrect to 
clear its  MSR_TS_MASK bits.....

Please correct me if I am wrong.

Thanks,
- Simon

  reply	other threads:[~2016-08-02  5:43 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-29  9:51 [PATCH] ppc64: allow ptrace to set TM bits Laurent Dufour
2016-08-02  5:43 ` Simon Guo [this message]
2016-08-17 14:40   ` Laurent Dufour
2016-08-22  1:01   ` Cyril Bur
2016-08-22  9:53     ` Laurent Dufour

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