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Date: Tue, 2 Aug 2016 20:12:02 +0800
From: Peter Xu <peterx@redhat.com>
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Subject: Re: [Qemu-devel] [PULL v5 29/57] intel_iommu: add SID validation
 for IR
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To: David Kiarie <davidkiarie4@gmail.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>, QEMU Developers <qemu-devel@nongnu.org>, "Michael S. Tsirkin" <mst@redhat.com>, Peter Maydell <peter.maydell@linaro.org>, Richard Henderson <rth@twiddle.net>, Eduardo Habkost <ehabkost@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>, Valentine Sinitsyn <valentine.sinitsyn@gmail.com>

On Tue, Aug 02, 2016 at 02:58:55PM +0300, David Kiarie wrote:
> > Sure. David, so do you like to do it or I cook this patch? :)
> 
> If there are no objections I will look at this employing Jan's approach:
> associating a write with an address space.

Do you mean to translate current stl_le_phys() into something like
address_space_stl_le(), with MemTxAttrs? (in ioapic_service())

Also, IIUC we also need to tweak a little bit more for split irqchip
case in kvm_arch_fixup_msi_route(). Actually for this one, I think
maybe we can assume the requester ID be IOAPIC's when dev == NULL,
since HPET should not be using kernel irqchip, right?

Thanks,

-- peterx