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* [Qemu-devel] [Bug 1611394] [NEW] qemu-ppc: Scalar Single-Precision Floating-Point instructions should not test MSR[SPV]
@ 2016-08-09 14:20 Andreas Rasmusson
  2020-07-25  2:56 ` [Bug 1611394] " Matthieu Bucchianeri
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Andreas Rasmusson @ 2016-08-09 14:20 UTC (permalink / raw)
  To: qemu-devel

Public bug reported:

According to "Signal Processing Engine (SPE) Programming Environments Manual" at
http://cache.nxp.com/files/32bit/doc/ref_manual/SPEPEM.pdf?fsrch=1&sr=1&pageNum=1

c.f section 4.2.3  and also Figure 2-2.

When MSR[SPV] is _NOT_ set, then the embedded scalar single-precision floating-point instructions
should _NOT_ generate an Embedded Floating-Point Unavailable Interrupt.


Hence, some tests for MSR[SPV] in file target-ppc/translate.c need to be removed.
Namely, in the definitions of 
1. GEN_SPEFPUOP_ARITH2_32_32
2. gen_efsabs
3. gen_efsnabs
4. gen_efsneg
5. GEN_SPEFPUOP_COMP_32

Note, the macro GEN_SPEFPUOP_CONV_32_32 is already correct.

One more thing, afaict the macro GEN_SPEFPUOP_CONV_32_64 is used by both
efs- and efd- instructions, and will need to be split in two versions.
The efs-use (i.e for efscfd) should be as it is today, but the use by efd-instructions 
(e.g efdctui) will need to add a test for MSR[SPV].


(I've looked at today's HEAD-revision of target-ppc/translate.c).

** Affects: qemu
     Importance: Undecided
         Status: New


** Tags: embedded floating-point ppc

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https://bugs.launchpad.net/bugs/1611394

Title:
  qemu-ppc: Scalar Single-Precision Floating-Point instructions should
  not test  MSR[SPV]

Status in QEMU:
  New

Bug description:
  According to "Signal Processing Engine (SPE) Programming Environments Manual" at
  http://cache.nxp.com/files/32bit/doc/ref_manual/SPEPEM.pdf?fsrch=1&sr=1&pageNum=1

  c.f section 4.2.3  and also Figure 2-2.

  When MSR[SPV] is _NOT_ set, then the embedded scalar single-precision floating-point instructions
  should _NOT_ generate an Embedded Floating-Point Unavailable Interrupt.

  
  Hence, some tests for MSR[SPV] in file target-ppc/translate.c need to be removed.
  Namely, in the definitions of 
  1. GEN_SPEFPUOP_ARITH2_32_32
  2. gen_efsabs
  3. gen_efsnabs
  4. gen_efsneg
  5. GEN_SPEFPUOP_COMP_32

  Note, the macro GEN_SPEFPUOP_CONV_32_32 is already correct.

  One more thing, afaict the macro GEN_SPEFPUOP_CONV_32_64 is used by both
  efs- and efd- instructions, and will need to be split in two versions.
  The efs-use (i.e for efscfd) should be as it is today, but the use by efd-instructions 
  (e.g efdctui) will need to add a test for MSR[SPV].


  (I've looked at today's HEAD-revision of target-ppc/translate.c).

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1611394/+subscriptions

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Bug 1611394] Re: qemu-ppc: Scalar Single-Precision Floating-Point instructions should not test MSR[SPV]
  2016-08-09 14:20 [Qemu-devel] [Bug 1611394] [NEW] qemu-ppc: Scalar Single-Precision Floating-Point instructions should not test MSR[SPV] Andreas Rasmusson
@ 2020-07-25  2:56 ` Matthieu Bucchianeri
  2020-07-25 19:41 ` Matthieu Bucchianeri
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Matthieu Bucchianeri @ 2020-07-25  2:56 UTC (permalink / raw)
  To: qemu-devel

I have filed a broader ticket, Bug #1888918, reporting a very similar
issue that leads to corruption/bad arithmetic when using double-
precision & vector instructions.

I will be submitting a patch in the next few days that will also address
this ticket.

-- 
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1611394

Title:
  qemu-ppc: Scalar Single-Precision Floating-Point instructions should
  not test  MSR[SPV]

Status in QEMU:
  New

Bug description:
  According to "Signal Processing Engine (SPE) Programming Environments Manual" at
  http://cache.nxp.com/files/32bit/doc/ref_manual/SPEPEM.pdf?fsrch=1&sr=1&pageNum=1

  c.f section 4.2.3  and also Figure 2-2.

  When MSR[SPV] is _NOT_ set, then the embedded scalar single-precision floating-point instructions
  should _NOT_ generate an Embedded Floating-Point Unavailable Interrupt.

  
  Hence, some tests for MSR[SPV] in file target-ppc/translate.c need to be removed.
  Namely, in the definitions of 
  1. GEN_SPEFPUOP_ARITH2_32_32
  2. gen_efsabs
  3. gen_efsnabs
  4. gen_efsneg
  5. GEN_SPEFPUOP_COMP_32

  Note, the macro GEN_SPEFPUOP_CONV_32_32 is already correct.

  One more thing, afaict the macro GEN_SPEFPUOP_CONV_32_64 is used by both
  efs- and efd- instructions, and will need to be split in two versions.
  The efs-use (i.e for efscfd) should be as it is today, but the use by efd-instructions 
  (e.g efdctui) will need to add a test for MSR[SPV].


  (I've looked at today's HEAD-revision of target-ppc/translate.c).

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1611394/+subscriptions


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Bug 1611394] Re: qemu-ppc: Scalar Single-Precision Floating-Point instructions should not test MSR[SPV]
  2016-08-09 14:20 [Qemu-devel] [Bug 1611394] [NEW] qemu-ppc: Scalar Single-Precision Floating-Point instructions should not test MSR[SPV] Andreas Rasmusson
  2020-07-25  2:56 ` [Bug 1611394] " Matthieu Bucchianeri
@ 2020-07-25 19:41 ` Matthieu Bucchianeri
  2020-11-04 22:53 ` John Snow
  2020-12-10  8:48 ` Thomas Huth
  3 siblings, 0 replies; 5+ messages in thread
From: Matthieu Bucchianeri @ 2020-07-25 19:41 UTC (permalink / raw)
  To: qemu-devel

** Changed in: qemu
     Assignee: (unassigned) => Matthieu Bucchianeri (matthieu-bucchianeri)

** Changed in: qemu
       Status: New => In Progress

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1611394

Title:
  qemu-ppc: Scalar Single-Precision Floating-Point instructions should
  not test  MSR[SPV]

Status in QEMU:
  In Progress

Bug description:
  According to "Signal Processing Engine (SPE) Programming Environments Manual" at
  http://cache.nxp.com/files/32bit/doc/ref_manual/SPEPEM.pdf?fsrch=1&sr=1&pageNum=1

  c.f section 4.2.3  and also Figure 2-2.

  When MSR[SPV] is _NOT_ set, then the embedded scalar single-precision floating-point instructions
  should _NOT_ generate an Embedded Floating-Point Unavailable Interrupt.

  
  Hence, some tests for MSR[SPV] in file target-ppc/translate.c need to be removed.
  Namely, in the definitions of 
  1. GEN_SPEFPUOP_ARITH2_32_32
  2. gen_efsabs
  3. gen_efsnabs
  4. gen_efsneg
  5. GEN_SPEFPUOP_COMP_32

  Note, the macro GEN_SPEFPUOP_CONV_32_32 is already correct.

  One more thing, afaict the macro GEN_SPEFPUOP_CONV_32_64 is used by both
  efs- and efd- instructions, and will need to be split in two versions.
  The efs-use (i.e for efscfd) should be as it is today, but the use by efd-instructions 
  (e.g efdctui) will need to add a test for MSR[SPV].


  (I've looked at today's HEAD-revision of target-ppc/translate.c).

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1611394/+subscriptions


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Bug 1611394] Re: qemu-ppc: Scalar Single-Precision Floating-Point instructions should not test MSR[SPV]
  2016-08-09 14:20 [Qemu-devel] [Bug 1611394] [NEW] qemu-ppc: Scalar Single-Precision Floating-Point instructions should not test MSR[SPV] Andreas Rasmusson
  2020-07-25  2:56 ` [Bug 1611394] " Matthieu Bucchianeri
  2020-07-25 19:41 ` Matthieu Bucchianeri
@ 2020-11-04 22:53 ` John Snow
  2020-12-10  8:48 ` Thomas Huth
  3 siblings, 0 replies; 5+ messages in thread
From: John Snow @ 2020-11-04 22:53 UTC (permalink / raw)
  To: qemu-devel

Assuming that this commit:
https://gitlab.com/qemu-project/qemu/-/commit/8dcdb535d7cc4ba6270bb756e12e1d323254ed4e

is sufficient to mark this bug as Fix Committed. Please re-open if I am
mistaken.

** Changed in: qemu
       Status: In Progress => Fix Committed

-- 
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1611394

Title:
  qemu-ppc: Scalar Single-Precision Floating-Point instructions should
  not test  MSR[SPV]

Status in QEMU:
  Fix Committed

Bug description:
  According to "Signal Processing Engine (SPE) Programming Environments Manual" at
  http://cache.nxp.com/files/32bit/doc/ref_manual/SPEPEM.pdf?fsrch=1&sr=1&pageNum=1

  c.f section 4.2.3  and also Figure 2-2.

  When MSR[SPV] is _NOT_ set, then the embedded scalar single-precision floating-point instructions
  should _NOT_ generate an Embedded Floating-Point Unavailable Interrupt.

  
  Hence, some tests for MSR[SPV] in file target-ppc/translate.c need to be removed.
  Namely, in the definitions of 
  1. GEN_SPEFPUOP_ARITH2_32_32
  2. gen_efsabs
  3. gen_efsnabs
  4. gen_efsneg
  5. GEN_SPEFPUOP_COMP_32

  Note, the macro GEN_SPEFPUOP_CONV_32_32 is already correct.

  One more thing, afaict the macro GEN_SPEFPUOP_CONV_32_64 is used by both
  efs- and efd- instructions, and will need to be split in two versions.
  The efs-use (i.e for efscfd) should be as it is today, but the use by efd-instructions 
  (e.g efdctui) will need to add a test for MSR[SPV].


  (I've looked at today's HEAD-revision of target-ppc/translate.c).

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1611394/+subscriptions


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Bug 1611394] Re: qemu-ppc: Scalar Single-Precision Floating-Point instructions should not test MSR[SPV]
  2016-08-09 14:20 [Qemu-devel] [Bug 1611394] [NEW] qemu-ppc: Scalar Single-Precision Floating-Point instructions should not test MSR[SPV] Andreas Rasmusson
                   ` (2 preceding siblings ...)
  2020-11-04 22:53 ` John Snow
@ 2020-12-10  8:48 ` Thomas Huth
  3 siblings, 0 replies; 5+ messages in thread
From: Thomas Huth @ 2020-12-10  8:48 UTC (permalink / raw)
  To: qemu-devel

Released with QEMU v5.2.0.

** Changed in: qemu
       Status: Fix Committed => Fix Released

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1611394

Title:
  qemu-ppc: Scalar Single-Precision Floating-Point instructions should
  not test  MSR[SPV]

Status in QEMU:
  Fix Released

Bug description:
  According to "Signal Processing Engine (SPE) Programming Environments Manual" at
  http://cache.nxp.com/files/32bit/doc/ref_manual/SPEPEM.pdf?fsrch=1&sr=1&pageNum=1

  c.f section 4.2.3  and also Figure 2-2.

  When MSR[SPV] is _NOT_ set, then the embedded scalar single-precision floating-point instructions
  should _NOT_ generate an Embedded Floating-Point Unavailable Interrupt.

  
  Hence, some tests for MSR[SPV] in file target-ppc/translate.c need to be removed.
  Namely, in the definitions of 
  1. GEN_SPEFPUOP_ARITH2_32_32
  2. gen_efsabs
  3. gen_efsnabs
  4. gen_efsneg
  5. GEN_SPEFPUOP_COMP_32

  Note, the macro GEN_SPEFPUOP_CONV_32_32 is already correct.

  One more thing, afaict the macro GEN_SPEFPUOP_CONV_32_64 is used by both
  efs- and efd- instructions, and will need to be split in two versions.
  The efs-use (i.e for efscfd) should be as it is today, but the use by efd-instructions 
  (e.g efdctui) will need to add a test for MSR[SPV].


  (I've looked at today's HEAD-revision of target-ppc/translate.c).

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1611394/+subscriptions


^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2020-12-10  9:15 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-08-09 14:20 [Qemu-devel] [Bug 1611394] [NEW] qemu-ppc: Scalar Single-Precision Floating-Point instructions should not test MSR[SPV] Andreas Rasmusson
2020-07-25  2:56 ` [Bug 1611394] " Matthieu Bucchianeri
2020-07-25 19:41 ` Matthieu Bucchianeri
2020-11-04 22:53 ` John Snow
2020-12-10  8:48 ` Thomas Huth

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