From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Sun, 14 Aug 2016 16:01:30 -0400 Subject: [U-Boot] [PATCH v4] arm: cache: always flush cache line size for page table In-Reply-To: References: <20160807174301.23482-1-stefan@agner.ch> Message-ID: <20160814200130.GJ4188@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Mon, Aug 08, 2016 at 12:43:03AM -0700, Stefan Agner wrote: > On 2016-08-07 23:10, Lokesh Vutla wrote: > > Hi, > > > > On Sunday 07 August 2016 11:13 PM, Stefan Agner wrote: > >> From: Stefan Agner > >> > >> The page table is maintained by the CPU, hence it is safe to always > >> align cache flush to a whole cache line size. This allows to use > >> mmu_page_table_flush for a single page table, e.g. when configure > >> only small regions through mmu_set_region_dcache_behaviour. > >> > >> Signed-off-by: Stefan Agner > >> Tested-by: Fabio Estevam > >> Reviewed-by: Simon Glass > >> --- > > > > I get the following warning when CONFIG_PHYS_64BIT is enabled on arm > > platforms(dra7xx_evm_defconfig): > > Hm, do I see things right, this is otherwise a 32-bit architecture? Does > that work without LPAE? What is the page table size in this case? It's a 32bit architecture with LPAE, iirc, yes. -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: