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From: "Radim Krčmář" <rkrcmar@redhat.com>
To: Wanpeng Li <kernellwp@gmail.com>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	kvm <kvm@vger.kernel.org>, Jim Mattson <jmattson@google.com>,
	Wincy Van <fanwenyi0529@gmail.com>,
	Paolo Bonzini <pbonzini@redhat.com>, Bandan Das <bsd@redhat.com>
Subject: Re: [PATCH 2/2] KVM: nVMX: postpone VMCS changes on MSR_IA32_APICBASE write
Date: Mon, 15 Aug 2016 16:31:52 +0200	[thread overview]
Message-ID: <20160815143152.GB12385@potion> (raw)
In-Reply-To: <CANRm+CzzrapdDv2okfpkKBxjbN_Yh-hbopXgaN1EfdNsvuBWTA@mail.gmail.com>

2016-08-15 13:19+0800, Wanpeng Li:
> 2016-08-12 19:39 GMT+08:00 Radim Krčmář <rkrcmar@redhat.com>:
>> 2016-08-12 18:14+0800, Wanpeng Li:
>>> 2016-08-12 17:44 GMT+08:00 Radim Krčmář <rkrcmar@redhat.com>:
>>>> 2016-08-12 14:07+0800, Wanpeng Li:
>>>>> 2016-08-09 2:16 GMT+08:00 Radim Krčmář <rkrcmar@redhat.com>:
>>>>>> If vmcs12 does not intercept APIC_BASE writes, then KVM will handle the
>>>>>> write with vmcs02 as the current VMCS.
>>>>>> This will incorrectly apply modifications intended for vmcs01 to vmcs02
>>>>>> and L2 can use it to gain access to L0's x2APIC registers by disabling
>>>>>> virtualized x2APIC while using msr bitmap that assumes enabled.
>>>>>>
>>>>>> Postpone execution of vmx_set_virtual_x2apic_mode until vmcs01 is the
>>>>>> current VMCS.  An alternative solution would temporarily make vmcs01 the
>>>>>> current VMCS, but it requires more care.
>>>>>
>>>>> There is a scenario both L1 and L2 are running on x2apic mode, L1
>>>>> don't own the APIC_BASE writes, then L2 is intended to disable x2apic
>>>>> mode, however, your logic will also disable x2apic mode for L1.
>>>>
>>>> You mean a case where L1 does intercept APIC_BASE?
>>>>
>>>> That case is not affected, because it should cause a nested VM exit, so
>>>> vmx_set_virtual_x2apic_mode() won't be called in the first place.
>>>
>>> I mean L1 doesn't intercept APIC_BASE.
>>
>> Then L2's write to APIC_BASE should only affect L1.
>> L2 is buggy if it intended to disable its x2APIC with the write
>> or L1 set up intercepts incorrectly for the indented L2.
> 
> Do you mean OS disable x2APIC during its running is buggy?

Not in general, but if L1 doesn't intercept APIC_BASE and L2 writes to
it in order to disable its (L2's) x2APIC, then there is a bug in L2 or
L1.

If L1 intended to intercept, then it's a clear L1 bug, otherwise L2
should have known that L1 is a special hypervisor that doesn't intercept
APIC_BASE and the bug is on L2 side or on the user that ran unsuspecting
L2 on that L1.

  reply	other threads:[~2016-08-15 14:31 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-08 18:16 [PATCH 0/2] KVM: nVMX: msr bitmaps fixes Radim Krčmář
2016-08-08 18:16 ` [PATCH 1/2] KVM: nVMX: fix msr bitmaps to prevent L2 from accessing L0 x2APIC Radim Krčmář
2016-08-09  9:32   ` Yang Zhang
2016-08-09 10:19     ` Wincy Van
2016-08-10  5:52       ` Yang Zhang
2016-08-09 12:23     ` Radim Krčmář
2016-08-10  5:55       ` Yang Zhang
2016-08-16  2:53   ` Wanpeng Li
2016-08-08 18:16 ` [PATCH 2/2] KVM: nVMX: postpone VMCS changes on MSR_IA32_APICBASE write Radim Krčmář
2016-08-12  6:07   ` Wanpeng Li
2016-08-12  9:44     ` Radim Krčmář
2016-08-12 10:14       ` Wanpeng Li
2016-08-12 11:39         ` Radim Krčmář
2016-08-15  5:19           ` Wanpeng Li
2016-08-15 14:31             ` Radim Krčmář [this message]
2016-08-16  2:43   ` Wanpeng Li

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