From: Bjorn Helgaas <bhelgaas@google.com>
To: Joao Pinto <Joao.Pinto@synopsys.com>
Cc: jszhang@marvell.com, jingoohan1@gmail.com,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: [PATCH v6 3/4] PCI: designware: Wait for iATU enable
Date: Wed, 17 Aug 2016 15:00:10 -0500 [thread overview]
Message-ID: <20160817200010.10418.85101.stgit@bhelgaas-glaptop2.roam.corp.google.com> (raw)
In-Reply-To: <20160817195239.10418.7037.stgit@bhelgaas-glaptop2.roam.corp.google.com>
From: Joao Pinto <Joao.Pinto@synopsys.com>
Add a loop with timeout to make sure the iATU is really enabled before
subsequent config and I/O accesses.
[bhelgaas: split to separate patch, use dev_err() instead of dev_dbg()]
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pcie-designware.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index e99f56e..947fac3 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -31,7 +31,12 @@
#define LINK_WAIT_USLEEP_MIN 90000
#define LINK_WAIT_USLEEP_MAX 100000
-/* Synopsis specific PCIE configuration registers */
+/* Parameters for the waiting for iATU enabled routine */
+#define LINK_WAIT_MAX_IATU_RETRIES 5
+#define LINK_WAIT_IATU_MIN 9000
+#define LINK_WAIT_IATU_MAX 10000
+
+/* Synopsys-specific PCIe configuration registers */
#define PCIE_PORT_LINK_CONTROL 0x710
#define PORT_LINK_MODE_MASK (0x3f << 16)
#define PORT_LINK_MODE_1_LANES (0x1 << 16)
@@ -157,7 +162,7 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
int type, u64 cpu_addr, u64 pci_addr, u32 size)
{
- u32 val;
+ u32 retries, val;
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
PCIE_ATU_VIEWPORT);
@@ -174,7 +179,14 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
* Make sure ATU enable takes effect before any subsequent config
* and I/O accesses.
*/
- val = dw_pcie_readl_rc(pp, PCIE_ATU_CR2);
+ for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
+ val = dw_pcie_readl_rc(pp, PCIE_ATU_CR2);
+ if (val == PCIE_ATU_ENABLE)
+ return;
+
+ usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
+ }
+ dev_err(pp->dev, "iATU is not being enabled\n");
}
static struct irq_chip dw_msi_irq_chip = {
next prev parent reply other threads:[~2016-08-17 20:00 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-17 19:59 [PATCH v6 0/4] pcie-designware: add iATU unroll feature Bjorn Helgaas
2016-08-17 19:59 ` [PATCH v6 1/4] PCI: designware: Return data directly from dw_pcie_readl_rc() Bjorn Helgaas
2016-08-17 19:59 ` [PATCH v6 2/4] PCI: designware: Move link wait definitions to .c file Bjorn Helgaas
2016-08-17 20:00 ` Bjorn Helgaas [this message]
2016-08-17 20:00 ` [PATCH v6 4/4] PCI: designware: Add iATU Unroll feature Bjorn Helgaas
2016-08-17 20:38 ` kbuild test robot
2016-11-16 0:22 ` Tim Harvey
2016-11-16 0:30 ` Fabio Estevam
2016-11-16 16:15 ` Tim Harvey
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