From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932807AbcHXOz6 (ORCPT ); Wed, 24 Aug 2016 10:55:58 -0400 Received: from mail.skyhub.de ([78.46.96.112]:60734 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755246AbcHXOzz (ORCPT ); Wed, 24 Aug 2016 10:55:55 -0400 Date: Wed, 24 Aug 2016 16:55:14 +0200 From: Borislav Petkov To: Matt Fleming Cc: Peter Zijlstra , linux-kernel@vger.kernel.org, Ingo Molnar , stable@vger.kernel.org Subject: Re: [PATCH v2] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Message-ID: <20160824145514.GA29210@nazgul.tnic> References: <1472044328-21302-1-git-send-email-matt@codeblueprint.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1472044328-21302-1-git-send-email-matt@codeblueprint.co.uk> User-Agent: Mutt/1.6.0 (2016-04-01) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 24, 2016 at 02:12:08PM +0100, Matt Fleming wrote: > While the Intel PMU monitors the LLC when perf enables the > HW_CACHE_REFERENCES and HW_CACHE_MISSES events, these events monitor > L1 instruction cache fetches (0x0080) and instruction cache misses > (0x0081) on the AMD PMU. > > This is extremely confusing when monitoring the same workload across > Intel and AMD machines, since parameters like, > > $ perf stat -e cache-references,cache-misses > > measure completely different things. > > Instead, make the AMD PMU measure instruction/data cache and TLB fill > requests to the L2 and instruction/data cache and TLB misses in the L2 > when HW_CACHE_REFERENCES and HW_CACHE_MISSES are enabled, > respectively. That way the events measure unified caches on both > platforms. I'm still not really sure about this: we can't really compare L3 to L2 access patterns - it is almost as comparing apples to oranges. Can we use the Intel L2 events instead? I mean, this makes much more sense to me because: * you *actually* compare the same cache levels * you have L2 *everywhere* vs L3 (and L4) which are sometimes not present on thin clients People who want LLC can enable them with -e additionally... Hmmm. -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. --