From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36441) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi0hp-0000pn-5f for qemu-devel@nongnu.org; Thu, 08 Sep 2016 10:53:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bi0hl-0000hi-Hw for qemu-devel@nongnu.org; Thu, 08 Sep 2016 10:53:32 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:29781) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bi0hl-0000ha-Bc for qemu-devel@nongnu.org; Thu, 08 Sep 2016 10:53:29 -0400 From: Paul Burton Date: Thu, 8 Sep 2016 15:51:54 +0100 Message-ID: <20160908145158.30720-5-paul.burton@imgtec.com> In-Reply-To: <20160908145158.30720-1-paul.burton@imgtec.com> References: <20160908145158.30720-1-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 4/8] target-mips: Provide function to test if a CPU supports an ISA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Aurelien Jarno , Leon Alrae Cc: Paul Burton Provide a new cpu_supports_isa function which allows callers to determine whether a CPU supports one of the ISA_ flags, by testing whether the associated struct mips_def_t sets the ISA flags in its insn_flags field. An example use of this is to allow boards which generate bootloader code to determine the properties of the CPU that will be used, for example whether the CPU is 64 bit or which architecture revision it implements. Signed-off-by: Paul Burton Reviewed-by: Leon Alrae --- target-mips/cpu.h | 1 + target-mips/translate.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 5182dc7..cbd17df 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -812,6 +812,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model)) bool cpu_supports_cps_smp(const char *cpu_model); +bool cpu_supports_isa(const char *cpu_model, unsigned int isa); void cpu_set_exception_base(int vp_index, target_ulong address); /* TODO QOM'ify CPU reset and remove */ diff --git a/target-mips/translate.c b/target-mips/translate.c index bab52cb..c212e4f 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -20192,6 +20192,16 @@ bool cpu_supports_cps_smp(const char *cpu_model) return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; } +bool cpu_supports_isa(const char *cpu_model, unsigned int isa) +{ + const mips_def_t *def = cpu_mips_find_by_name(cpu_model); + if (!def) { + return false; + } + + return (def->insn_flags & isa) != 0; +} + void cpu_set_exception_base(int vp_index, target_ulong address) { MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); -- 2.9.3