From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753068AbcIIJLZ (ORCPT ); Fri, 9 Sep 2016 05:11:25 -0400 Received: from foss.arm.com ([217.140.101.70]:36456 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750710AbcIIJLX (ORCPT ); Fri, 9 Sep 2016 05:11:23 -0400 Date: Fri, 9 Sep 2016 10:10:52 +0100 From: Mark Rutland To: "S.H. Xie" Cc: "devicetree@vger.kernel.org" , "robh+dt@kernel.org" , "linux-arm-kernel@lists.infradead.org" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "shawnguo@kernel.org" , "linux-kernel@vger.kernel.org" , "arnd@arndb.de" , Vincent Hu , Horia Geanta Neag , Mihai Emilian Bantea , "C.H. Zhao" , "Q.Y. Gong" , "M.H. Lian" , "Z.Q. Hou" Subject: Re: [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support Message-ID: <20160909091052.GA10562@leverpostej> References: <1473069695-33092-1-git-send-email-shh.xie@gmail.com> <1473069695-33092-4-git-send-email-shh.xie@gmail.com> <20160908131326.GE26570@leverpostej> <20160908131818.GF26570@leverpostej> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 09, 2016 at 06:55:30AM +0000, S.H. Xie wrote: > > On Thu, Sep 08, 2016 at 02:13:26PM +0100, Mark Rutland wrote: > > > On Mon, Sep 05, 2016 at 06:01:31PM +0800, shh.xie@gmail.com wrote: > > > > + cpus { > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + > > > > + cpu0: cpu@0 { > > > > + device_type = "cpu"; > > > > + compatible = "arm,cortex-a72"; > > > > + reg = <0x0>; > > > > + clocks = <&clockgen 1 0>; > > > > + next-level-cache = <&l2>; > > > > + cpu-idle-states = <&CPU_PH20>; > > > > + }; > > > > > > [...] > > > > > > > + }; > > > > + > > > > + idle-states { > > > > + entry-method = "arm,psci"; > > > > + > > > > + CPU_PH20: cpu-ph20 { > > > > + compatible = "arm,idle-state"; > > > > + idle-state-name = "PH20"; > > > > + arm,psci-suspend-param = <0x00010000>; > > > > + entry-latency-us = <1000>; > > > > + exit-latency-us = <1000>; > > > > + min-residency-us = <3000>; > > > > + }; > > > > + }; > > > > > > There's no PSCI node in this file, and none from am included file, so > > > this doesn't look right. > > > > Looking again, none of the cpu nodes has an enable-method property, and > > subsequent patches don't seem to add that to any cpu node. > > > > Has this DT actually been tested? > [S.H] The PSCI node and the enable-method property are added by U-boot. > U-boot can determine if using PSCI. If U-boot enables PSCI, it will add these > missed parts in the dts. If not, it will not add these missed parts, > so kernel will not use PSCI. > > In other words, the dts does not enable PSCI by default. > It's U-boot which adds the missed part if it determines to use PSCI. Ok. Could you please place a comment in the dts to that effect? Thanks, Mark. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark Rutland Subject: Re: [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support Date: Fri, 9 Sep 2016 10:10:52 +0100 Message-ID: <20160909091052.GA10562@leverpostej> References: <1473069695-33092-1-git-send-email-shh.xie@gmail.com> <1473069695-33092-4-git-send-email-shh.xie@gmail.com> <20160908131326.GE26570@leverpostej> <20160908131818.GF26570@leverpostej> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: "S.H. Xie" Cc: "devicetree@vger.kernel.org" , "robh+dt@kernel.org" , "linux-arm-kernel@lists.infradead.org" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "shawnguo@kernel.org" , "linux-kernel@vger.kernel.org" , "arnd@arndb.de" , Vincent Hu , Horia Geanta Neag , Mihai Emilian Bantea , "C.H. Zhao" , "Q.Y. Gong" , "M.H. Lian" , "Z.Q. Hou" List-Id: devicetree@vger.kernel.org On Fri, Sep 09, 2016 at 06:55:30AM +0000, S.H. Xie wrote: > > On Thu, Sep 08, 2016 at 02:13:26PM +0100, Mark Rutland wrote: > > > On Mon, Sep 05, 2016 at 06:01:31PM +0800, shh.xie@gmail.com wrote: > > > > + cpus { > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + > > > > + cpu0: cpu@0 { > > > > + device_type = "cpu"; > > > > + compatible = "arm,cortex-a72"; > > > > + reg = <0x0>; > > > > + clocks = <&clockgen 1 0>; > > > > + next-level-cache = <&l2>; > > > > + cpu-idle-states = <&CPU_PH20>; > > > > + }; > > > > > > [...] > > > > > > > + }; > > > > + > > > > + idle-states { > > > > + entry-method = "arm,psci"; > > > > + > > > > + CPU_PH20: cpu-ph20 { > > > > + compatible = "arm,idle-state"; > > > > + idle-state-name = "PH20"; > > > > + arm,psci-suspend-param = <0x00010000>; > > > > + entry-latency-us = <1000>; > > > > + exit-latency-us = <1000>; > > > > + min-residency-us = <3000>; > > > > + }; > > > > + }; > > > > > > There's no PSCI node in this file, and none from am included file, so > > > this doesn't look right. > > > > Looking again, none of the cpu nodes has an enable-method property, and > > subsequent patches don't seem to add that to any cpu node. > > > > Has this DT actually been tested? > [S.H] The PSCI node and the enable-method property are added by U-boot. > U-boot can determine if using PSCI. If U-boot enables PSCI, it will add these > missed parts in the dts. If not, it will not add these missed parts, > so kernel will not use PSCI. > > In other words, the dts does not enable PSCI by default. > It's U-boot which adds the missed part if it determines to use PSCI. Ok. Could you please place a comment in the dts to that effect? Thanks, Mark. From mboxrd@z Thu Jan 1 00:00:00 1970 From: mark.rutland@arm.com (Mark Rutland) Date: Fri, 9 Sep 2016 10:10:52 +0100 Subject: [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support In-Reply-To: References: <1473069695-33092-1-git-send-email-shh.xie@gmail.com> <1473069695-33092-4-git-send-email-shh.xie@gmail.com> <20160908131326.GE26570@leverpostej> <20160908131818.GF26570@leverpostej> Message-ID: <20160909091052.GA10562@leverpostej> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Sep 09, 2016 at 06:55:30AM +0000, S.H. Xie wrote: > > On Thu, Sep 08, 2016 at 02:13:26PM +0100, Mark Rutland wrote: > > > On Mon, Sep 05, 2016 at 06:01:31PM +0800, shh.xie at gmail.com wrote: > > > > + cpus { > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + > > > > + cpu0: cpu at 0 { > > > > + device_type = "cpu"; > > > > + compatible = "arm,cortex-a72"; > > > > + reg = <0x0>; > > > > + clocks = <&clockgen 1 0>; > > > > + next-level-cache = <&l2>; > > > > + cpu-idle-states = <&CPU_PH20>; > > > > + }; > > > > > > [...] > > > > > > > + }; > > > > + > > > > + idle-states { > > > > + entry-method = "arm,psci"; > > > > + > > > > + CPU_PH20: cpu-ph20 { > > > > + compatible = "arm,idle-state"; > > > > + idle-state-name = "PH20"; > > > > + arm,psci-suspend-param = <0x00010000>; > > > > + entry-latency-us = <1000>; > > > > + exit-latency-us = <1000>; > > > > + min-residency-us = <3000>; > > > > + }; > > > > + }; > > > > > > There's no PSCI node in this file, and none from am included file, so > > > this doesn't look right. > > > > Looking again, none of the cpu nodes has an enable-method property, and > > subsequent patches don't seem to add that to any cpu node. > > > > Has this DT actually been tested? > [S.H] The PSCI node and the enable-method property are added by U-boot. > U-boot can determine if using PSCI. If U-boot enables PSCI, it will add these > missed parts in the dts. If not, it will not add these missed parts, > so kernel will not use PSCI. > > In other words, the dts does not enable PSCI by default. > It's U-boot which adds the missed part if it determines to use PSCI. Ok. Could you please place a comment in the dts to that effect? Thanks, Mark.