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Date:   Wed, 21 Sep 2016 15:08:52 +0200
From:   Ralf Baechle <ralf@linux-mips.org>
To:     James Hogan <james.hogan@imgtec.com>
Cc:     Matt Redfearn <matt.redfearn@imgtec.com>, linux-mips@linux-mips.org
Subject: Re: [PATCH 1/9] MIPS: traps: 64bit kernels should read CP0_EBase
 64bit
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On Thu, Sep 01, 2016 at 05:30:07PM +0100, James Hogan wrote:

> When reading the CP0_EBase register containing the WG (write gate) bit,
> the ebase variable should be set to the full value of the register, i.e.
> on a 64-bit kernel the full 64-bit width of the register via
> read_cp0_ebase_64(), and on a 32-bit kernel the full 32-bit width
> including bits 31:30 which may be writeable.

How about changing the definition of read/write_c0_ebase to

#define read_c0_ebase()         __read_ulong_c0_register($15, 1)
#define write_c0_ebase(val)     __write_ulong_c0_register($15, 1, val)

or using a new variant like

#define read_c0_ebase_ulong()         __read_ulong_c0_register($15, 1)
#define write_c0_ebase_ulong(val)     __write_ulong_c0_register($15, 1, val)

to avoid the ifdefery?  This could also make this bit

                ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
                                         : (s32)read_c0_ebase();

in cpu-probe.c prettier.

  Ralf