From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760508AbcIWXzH (ORCPT ); Fri, 23 Sep 2016 19:55:07 -0400 Received: from mail.kernel.org ([198.145.29.136]:36662 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757343AbcIWXzF (ORCPT ); Fri, 23 Sep 2016 19:55:05 -0400 Date: Fri, 23 Sep 2016 18:55:00 -0500 From: Bjorn Helgaas To: Brian Norris Cc: Bjorn Helgaas , linux-kernel@vger.kernel.org, Shawn Lin , devicetree@vger.kernel.org, Jeffy Chen , Wenrui Li , Heiko Stuebner , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org Subject: Re: [PATCH] PCI: rockchip: Support quirk to disable 5 GT/s (PCIe 2.x) link rate Message-ID: <20160923235500.GA3569@localhost> References: <1474565478-27242-1-git-send-email-briannorris@chromium.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1474565478-27242-1-git-send-email-briannorris@chromium.org> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 22, 2016 at 10:31:18AM -0700, Brian Norris wrote: > rk3399 supports PCIe 2.x link speeds marginally at best, and on some > boards, the link won't train at 5 GT/s at all. Rather than sacrifice 500 > ms waiting for training that will never happen, let's support a device > tree quirk flag to disable generation 2 speeds entirely. > > Signed-off-by: Brian Norris > --- > .../devicetree/bindings/pci/rockchip-pcie.txt | 2 + > drivers/pci/host/pcie-rockchip.c | 57 +++++++++++++--------- > 2 files changed, 37 insertions(+), 22 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > index ba67b39939c1..e769726fd093 100644 > --- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > @@ -42,6 +42,8 @@ Required properties: > Optional Property: > - ep-gpios: contain the entry for pre-reset gpio > - num-lanes: number of lanes to use > +- rockchip,disable-gen2: present if PCIe generation 2.x (i.e., 5 GT/s link > + speeds) is not supported. > - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe. > - vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe. > - vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe. We already have st,pcie-is-gen1 and fsl,max-link-speed for similar issues. Can you copy the naming of one of those? The "max-link-speed" one seems a little more general. Bjorn