On Thu, Oct 06, 2016 at 05:18:26PM +0100, Maciej W. Rozycki wrote:
> Hi James,
> 
> > >  This does look wrong to me, as I noted above EBase is 64-bit with MIPS64 
> > > processors as from architecture revision 3.50.  Also I don't think we want 
> > 
> > MIPS64 PRA (I'm looking at r5 and r6) seems to allow for write-gate not
> > to be implemented, in which case the register is only 32-bits.
> 
>  Indeed, but we need to be prepared to handle the width of 64 bits and 
> `cpu_has_mips64r6' does not seem to me to be the right condition.

The relevance of r6 is the assurance that reading a 32-bit COP0 register
with dmfc0 is no longer UNDEFINED (like r5 and before), but reads the
top 32-bits as reserved, i.e. read zero (may need manual sign
extension) and writes ignored.

> 
>  ISTR a while ago we had a rather lengthy discussion as to how to detect 
> the presence of the upper 32 bits without triggering undefined behaviour 
> implied by 64-bit CP0 accesses to 32-bit CP0 registers.  As I believe we 
> set EBase ourselves I think we are able to make the necessary checks and 
> have an accurate condition here, still remembering however that it may go 
> back as far as MIPSr3.

We only set ebase under certain circumstances, otherwise leaving it as
already set.

Cheers
James