From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57859) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bsNQN-0005Xw-Eg for qemu-devel@nongnu.org; Fri, 07 Oct 2016 01:10:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bsNQK-0005qe-G3 for qemu-devel@nongnu.org; Fri, 07 Oct 2016 01:10:22 -0400 Date: Fri, 7 Oct 2016 15:34:46 +1100 From: David Gibson Message-ID: <20161007043446.GT18490@umbus.fritz.box> References: <1475479496-16158-1-git-send-email-clg@kaod.org> <1475479496-16158-5-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="T/yvDUeUQRtJzDrt" Content-Disposition: inline In-Reply-To: <1475479496-16158-5-git-send-email-clg@kaod.org> Subject: Re: [Qemu-devel] [PATCH v4 04/20] ppc/pnv: add a PIR handler to PnvChip List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org --T/yvDUeUQRtJzDrt Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Oct 03, 2016 at 09:24:40AM +0200, C=E9dric Le Goater wrote: > The Processor Identification Register (PIR) is a register that holds a > processor identifier which is used for bus transactions (XSCOM) and > for processor differentiation in multiprocessor systems. It also used > in the interrupt vector entries (IVE) to identify the thread serving > the interrupts. >=20 > P9 and P8 have some differences in the CPU PIR encoding. >=20 > Signed-off-by: C=E9dric Le Goater Reviewed-by: David Gibson Looks fine, although it's a bit hard to be sure since I haven't read the patches which actually use this yet. > --- >=20 > Changes since v3 : >=20 > - added a couple more comments on the bits definition > =20 > hw/ppc/pnv.c | 30 ++++++++++++++++++++++++++++++ > include/hw/ppc/pnv.h | 2 ++ > 2 files changed, 32 insertions(+) >=20 > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index fc930be94f53..758c849702a0 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -239,6 +239,32 @@ static void ppc_powernv_init(MachineState *machine) > g_free(chip_typename); > } > =20 > +/* > + * 0:21 Reserved - Read as zeros > + * 22:24 Chip ID > + * 25:28 Core number > + * 29:31 Thread ID > + */ > +static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) > +{ > + return (chip->chip_id << 7) | (core_id << 3); > +} > + > +/* > + * 0:48 Reserved - Read as zeroes > + * 49:52 Node ID > + * 53:55 Chip ID > + * 56 Reserved - Read as zero > + * 57:61 Core number > + * 62:63 Thread ID > + * > + * We only care about the lower bits. uint32_t is fine for the moment. > + */ > +static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) > +{ > + return (chip->chip_id << 8) | (core_id << 2); > +} > + > /* Allowed core identifiers on a POWER8 Processor Chip : > * > * > @@ -274,6 +300,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *= klass, void *data) > k->chip_type =3D PNV_CHIP_POWER8E; > k->chip_cfam_id =3D 0x221ef04980000000ull; /* P8 Murano DD2.1 */ > k->cores_mask =3D POWER8E_CORE_MASK; > + k->core_pir =3D pnv_chip_core_pir_p8; > dc->desc =3D "PowerNV Chip POWER8E"; > } > =20 > @@ -293,6 +320,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) > k->chip_type =3D PNV_CHIP_POWER8; > k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */ > k->cores_mask =3D POWER8_CORE_MASK; > + k->core_pir =3D pnv_chip_core_pir_p8; > dc->desc =3D "PowerNV Chip POWER8"; > } > =20 > @@ -312,6 +340,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) > k->chip_type =3D PNV_CHIP_POWER8NVL; > k->chip_cfam_id =3D 0x120d304980000000ull; /* P8 Naples DD1.0 */ > k->cores_mask =3D POWER8_CORE_MASK; > + k->core_pir =3D pnv_chip_core_pir_p8; > dc->desc =3D "PowerNV Chip POWER8NVL"; > } > =20 > @@ -331,6 +360,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) > k->chip_type =3D PNV_CHIP_POWER9; > k->chip_cfam_id =3D 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ > k->cores_mask =3D POWER9_CORE_MASK; > + k->core_pir =3D pnv_chip_core_pir_p9; > dc->desc =3D "PowerNV Chip POWER9"; > } > =20 > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index 2c225c928974..c676f800e28e 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -56,6 +56,8 @@ typedef struct PnvChipClass { > PnvChipType chip_type; > uint64_t chip_cfam_id; > uint64_t cores_mask; > + > + uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); > } PnvChipClass; > =20 > #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E" --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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