From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47541) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bsUqi-0001u2-1K for qemu-devel@nongnu.org; Fri, 07 Oct 2016 09:06:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bsUqb-0000mR-ID for qemu-devel@nongnu.org; Fri, 07 Oct 2016 09:06:03 -0400 Received: from mx1.redhat.com ([209.132.183.28]:49624) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bsUqa-0000lg-UO for qemu-devel@nongnu.org; Fri, 07 Oct 2016 09:05:57 -0400 Date: Fri, 7 Oct 2016 15:05:53 +0200 From: Igor Mammedov Message-ID: <20161007150553.2e4ccc9a@nial.brq.redhat.com> In-Reply-To: <20161005130657.3399-4-rkrcmar@redhat.com> References: <20161005130657.3399-1-rkrcmar@redhat.com> <20161005130657.3399-4-rkrcmar@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v4 3/8] intel_iommu: pass whole remapped addresses to apic List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Radim =?UTF-8?B?S3LEjW3DocWZ?= Cc: qemu-devel@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , Peter Xu , Paolo Bonzini , Richard Henderson On Wed, 5 Oct 2016 15:06:52 +0200 Radim Kr=C4=8Dm=C3=A1=C5=99 wrote: > The MMIO interface to APIC only allowed 8 bit addresses, which is not > enough for 32 bit addresses from EIM remapping. > Intel stored upper 24 bits in the high MSI address, so use the same > technique. The technique is also used in KVM MSI interface. > Other APICs are unlikely to handle those upper bits. >=20 > Reviewed-by: Igor Mammedov I don't recall giving my RB to this patch but I do recall asking question, see below. > Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 > --- > v4: r-b Igor > v2: fix build with enabled DEBUG_INTEL_IOMMU [Peter] > --- > hw/i386/intel_iommu.c | 21 +++++++++------------ > 1 file changed, 9 insertions(+), 12 deletions(-) >=20 > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index 9f4e64af1ad5..c39b62b898d8 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -31,6 +31,7 @@ > #include "hw/i386/x86-iommu.h" > #include "hw/pci-host/q35.h" > #include "sysemu/kvm.h" > +#include "hw/i386/apic_internal.h" > =20 > /*#define DEBUG_INTEL_IOMMU*/ > #ifdef DEBUG_INTEL_IOMMU > @@ -279,18 +280,17 @@ static void vtd_update_iotlb(IntelIOMMUState *s, ui= nt16_t source_id, > static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_= reg, > hwaddr mesg_data_reg) > { > - hwaddr addr; > - uint32_t data; > + MSIMessage msi; > =20 > assert(mesg_data_reg < DMAR_REG_SIZE); > assert(mesg_addr_reg < DMAR_REG_SIZE); > =20 > - addr =3D vtd_get_long_raw(s, mesg_addr_reg); > - data =3D vtd_get_long_raw(s, mesg_data_reg); > + msi.address =3D vtd_get_long_raw(s, mesg_addr_reg); > + msi.data =3D vtd_get_long_raw(s, mesg_data_reg); > =20 > - VTD_DPRINTF(FLOG, "msi: addr 0x%"PRIx64 " data 0x%"PRIx32, addr, dat= a); > - address_space_stl_le(&address_space_memory, addr, data, > - MEMTXATTRS_UNSPECIFIED, NULL); > + VTD_DPRINTF(FLOG, "msi: addr 0x%"PRIx64 " data 0x%"PRIx32, > + msi.address, msi.data); > + apic_get_class()->send_msi(&msi); > } > =20 > /* Generate a fault event to software via MSI if conditions are met. > @@ -2133,6 +2133,7 @@ static void vtd_generate_msi_message(VTDIrq *irq, M= SIMessage *msg_out) > msg.dest_mode =3D irq->dest_mode; > msg.redir_hint =3D irq->redir_hint; > msg.dest =3D irq->dest; > + msg.__addr_hi =3D irq->dest & 0xffffff00; what about BE host? should it be: msg.__addr_hi =3D cpu_to_le32(irq->dest & 0xffffff00) > msg.__addr_head =3D cpu_to_le32(0xfee); > /* Keep this from original MSI address bits */ > msg.__not_used =3D irq->msi_addr_last_bits; > @@ -2281,11 +2282,7 @@ static MemTxResult vtd_mem_ir_write(void *opaque, = hwaddr addr, > " for device sid 0x%04x", > to.address, to.data, sid); > =20 > - if (dma_memory_write(&address_space_memory, to.address, > - &to.data, size)) { > - VTD_DPRINTF(GENERAL, "error: fail to write 0x%"PRIx64 > - " value 0x%"PRIx32, to.address, to.data); > - } > + apic_get_class()->send_msi(&to); > =20 > return MEMTX_OK; > }