From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44089) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1buwWW-0002D3-SL for qemu-devel@nongnu.org; Fri, 14 Oct 2016 03:03:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1buwWR-0005EL-S0 for qemu-devel@nongnu.org; Fri, 14 Oct 2016 03:03:20 -0400 Date: Fri, 14 Oct 2016 17:36:52 +1100 From: David Gibson Message-ID: <20161014063652.GU28562@umbus> References: <1475479496-16158-1-git-send-email-clg@kaod.org> <1475479496-16158-20-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="TVVcQco/7vcH19KK" Content-Disposition: inline In-Reply-To: <1475479496-16158-20-git-send-email-clg@kaod.org> Subject: Re: [Qemu-devel] [PATCH v4 19/20] ppc/pnv: Add Naples chip support for LPC interrupts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org --TVVcQco/7vcH19KK Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Oct 03, 2016 at 09:24:55AM +0200, C=E9dric Le Goater wrote: > From: Benjamin Herrenschmidt >=20 > It adds the Naples chip which supports proper LPC interrupts via the > LPC controller rather than via an external CPLD. >=20 > Signed-off-by: Benjamin Herrenschmidt > [clg: - updated for qemu-2.7 > - ported on latest PowerNV patchset (v3) ] > Signed-off-by: C=E9dric Le Goater > --- > hw/ppc/pnv.c | 18 +++++++++++++++++- > hw/ppc/pnv_lpc.c | 47 ++++++++++++++++++++++++++++++++++++++++++= +++-- > include/hw/ppc/pnv_lpc.h | 7 +++++++ > 3 files changed, 69 insertions(+), 3 deletions(-) >=20 > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index e805e97d4d87..5b70ccf66fac 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -340,7 +340,17 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaqu= e, int n, int level) > =20 > static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) > { > - /* XXX TODO */ > + PnvLpcController *lpc =3D opaque; > + > + if (n >=3D ISA_NUM_IRQS) { > + return; > + } How could n >=3D ISA_NUM_IRQS arise? Would it have to mean a bug elsewhere in your code? If so this should be an assert(). > + > + /* The Naples HW latches the 1 levels, clearing is done by SW */ > + if (level) { > + lpc->lpc_hc_irqstat |=3D LPC_HC_IRQ_SERIRQ0 >> n; > + pnv_lpc_eval_irqs(lpc); > + } > } > =20 > static ISABus *pnv_isa_create(PnvChip *chip) > @@ -656,6 +666,12 @@ static void pnv_chip_init(Object *obj) > object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); > object_property_add_const_link(OBJECT(&chip->occ), "psi", > OBJECT(&chip->psi), &error_abort); > + > + /* > + * The LPC controller needs PSI to generate interrupts > + */ > + object_property_add_const_link(OBJECT(&chip->lpc), "psi", > + OBJECT(&chip->psi), &error_abort); > } > =20 > static void pnv_chip_realize(DeviceState *dev, Error **errp) > diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c > index 210cc1cff167..8b78b0a1e414 100644 > --- a/hw/ppc/pnv_lpc.c > +++ b/hw/ppc/pnv_lpc.c > @@ -249,6 +249,34 @@ static const MemoryRegionOps pnv_lpc_xscom_ops =3D { > .endianness =3D DEVICE_BIG_ENDIAN, > }; > =20 > +void pnv_lpc_eval_irqs(PnvLpcController *lpc) > +{ > + bool lpc_to_opb_irq =3D false; > + > + /* Update LPC controller to OPB line */ > + if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) { > + uint32_t irqs; > + > + irqs =3D lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask; > + lpc_to_opb_irq =3D (irqs !=3D 0); > + } > + > + /* We don't honor the polarity register, it's pointless and unused > + * anyway > + */ > + if (lpc_to_opb_irq) { > + lpc->opb_irq_input |=3D OPB_MASTER_IRQ_LPC; > + } else { > + lpc->opb_irq_input &=3D ~OPB_MASTER_IRQ_LPC; > + } > + > + /* Update OPB internal latch */ > + lpc->opb_irq_stat |=3D lpc->opb_irq_input & lpc->opb_irq_mask; > + > + /* Reflect the interrupt */ > + pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat !=3D = 0); > +} > + > static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size) > { > PnvLpcController *lpc =3D opaque; > @@ -299,12 +327,15 @@ static void lpc_hc_write(void *opaque, hwaddr addr,= uint64_t val, > break; > case LPC_HC_IRQSER_CTRL: > lpc->lpc_hc_irqser_ctrl =3D val; > + pnv_lpc_eval_irqs(lpc); > break; > case LPC_HC_IRQMASK: > lpc->lpc_hc_irqmask =3D val; > + pnv_lpc_eval_irqs(lpc); > break; > case LPC_HC_IRQSTAT: > lpc->lpc_hc_irqstat &=3D ~val; > + pnv_lpc_eval_irqs(lpc); > break; > case LPC_HC_ERROR_ADDRESS: > break; > @@ -362,14 +393,15 @@ static void opb_master_write(void *opaque, hwaddr a= ddr, > switch (addr) { > case OPB_MASTER_LS_IRQ_STAT: > lpc->opb_irq_stat &=3D ~val; > + pnv_lpc_eval_irqs(lpc); > break; > case OPB_MASTER_LS_IRQ_MASK: > - /* XXX Filter out reserved bits */ > lpc->opb_irq_mask =3D val; > + pnv_lpc_eval_irqs(lpc); > break; > case OPB_MASTER_LS_IRQ_POL: > - /* XXX Filter out reserved bits */ > lpc->opb_irq_pol =3D val; > + pnv_lpc_eval_irqs(lpc); > break; > case OPB_MASTER_LS_IRQ_INPUT: > /* Read only */ > @@ -397,6 +429,8 @@ static const MemoryRegionOps opb_master_ops =3D { > static void pnv_lpc_realize(DeviceState *dev, Error **errp) > { > PnvLpcController *lpc =3D PNV_LPC(dev); > + Object *obj; > + Error *error =3D NULL; > =20 > /* Reg inits */ > lpc->lpc_hc_fw_rd_acc_size =3D LPC_HC_FW_RD_4B; > @@ -440,6 +474,15 @@ static void pnv_lpc_realize(DeviceState *dev, Error = **errp) > memory_region_init_io(&lpc->xscom_regs, OBJECT(dev), > &pnv_lpc_xscom_ops, lpc, "xscom-lpc", > PNV_XSCOM_LPC_SIZE << 3); > + > + /* get PSI object from chip */ > + obj =3D object_property_get_link(OBJECT(dev), "psi", &error); > + if (!obj) { > + error_setg(errp, "%s: required link 'psi' not found: %s", > + __func__, error_get_pretty(error)); > + return; > + } > + lpc->psi =3D PNV_PSI(obj); > } > =20 > static void pnv_lpc_class_init(ObjectClass *klass, void *data) > diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h > index 38e5506975aa..fc348dca50ca 100644 > --- a/include/hw/ppc/pnv_lpc.h > +++ b/include/hw/ppc/pnv_lpc.h > @@ -23,9 +23,13 @@ > #define PNV_LPC(obj) \ > OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC) > =20 > +typedef struct PnvPsiController PnvPsiController; > + > typedef struct PnvLpcController { > DeviceState parent; > =20 > + PnvPsiController *psi; > + > uint64_t eccb_stat_reg; > uint32_t eccb_data_reg; > =20 > @@ -64,4 +68,7 @@ typedef struct PnvLpcController { > MemoryRegion xscom_regs; > } PnvLpcController; > =20 > +#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to .= =2E. */ > +void pnv_lpc_eval_irqs(PnvLpcController *lpc); > + > #endif /* _PPC_PNV_LPC_H */ --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --TVVcQco/7vcH19KK Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJYAH0DAAoJEGw4ysog2bOSAmwP/jy8HE89F02yffPJhz3G2IGY sZhFPChcWBb62dzF5J85zu8SRbQwFZK7eHsHWfpdczyIsN+Bg3sRpCie1+qLy/DZ 4vATN+NNzWGzKOrAd61kcvgrfJCBF4cNe4nwZO+y4Ya2NICMMAX5IoBoqQYmxl75 /F25FwskTRLtnX/znsAAYnx7U+8FV69hjLnArpVwRHLlLaOrUYL8etFNhCJpbh1H JOicZyJ1ZmQ2t8CYUfmpV+PWQO3QuP3ccmWfKuaNhPu7C5q+WNj6skBVzTW+2hvk yuM5thJjyoDtiZCj6oNfLuV+LZSEUCUAUlQnU3D01VI2nqZyfAeKYzv3ySp3XyS1 E1cu3nf3nAkaPeqd14zEf7mHoKIvBYwZtC6e2PeCMeI1kaUA6WNq4zCWcxFsBjDy SlzUY+3bFceHZsaKeTVVFq0rsadiN/yg46MbK4YhwJl6aDWMjo6rNWBN+iZ67TmL GYeU/y3cehk+68FPc+dJy/K1GSR572GOjVyMqbq53aGYiQKDOPDBPhnDshW2WSut nZhE04QZVK/XO7NJoeEgj12PrRyjHX4sSEyJUjTjttP8t3PfMBLAI7lt47CgbgGG L+zx2CdXxZnNXGIbn+H856lrvrwoJJRwLhXsCCbe7d2qF3991+h9uB5/bfu3ImkM 5wKIYP3OOn2XB7vYmoNh =2863 -----END PGP SIGNATURE----- --TVVcQco/7vcH19KK--