From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965350AbcJQVeV (ORCPT ); Mon, 17 Oct 2016 17:34:21 -0400 Received: from mail.kmu-office.ch ([178.209.48.109]:48400 "EHLO mail.kmu-office.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965083AbcJQVds (ORCPT ); Mon, 17 Oct 2016 17:33:48 -0400 From: Stefan Agner To: meng.yi@nxp.com, dri-devel@lists.freedesktop.org Cc: alison.wang@freescale.com, jianwei.wang.chn@gmail.com, linux-kernel@vger.kernel.org, Stefan Agner Subject: [PATCH v3 3/5] drm/fsl-dcu: do not transfer registers in mode_set_nofb Date: Mon, 17 Oct 2016 14:33:19 -0700 Message-Id: <20161017213321.8074-4-stefan@agner.ch> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20161017213321.8074-1-stefan@agner.ch> References: <20161017213321.8074-1-stefan@agner.ch> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Do not schedule a transfer of mode settings early. Modes should get applied on on CRTC enable where we also enable the pixel clock. Signed-off-by: Stefan Agner --- drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c index 3371635..5ad1d68 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c @@ -116,8 +116,6 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) | DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) | DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL)); - regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, - DCU_UPDATE_MODE_READREG); return; } -- 2.10.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Agner Subject: [PATCH v3 3/5] drm/fsl-dcu: do not transfer registers in mode_set_nofb Date: Mon, 17 Oct 2016 14:33:19 -0700 Message-ID: <20161017213321.8074-4-stefan@agner.ch> References: <20161017213321.8074-1-stefan@agner.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail.kmu-office.ch (mail.kmu-office.ch [178.209.48.109]) by gabe.freedesktop.org (Postfix) with ESMTPS id 971666E5C7 for ; Mon, 17 Oct 2016 21:33:48 +0000 (UTC) In-Reply-To: <20161017213321.8074-1-stefan@agner.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: meng.yi@nxp.com, dri-devel@lists.freedesktop.org Cc: jianwei.wang.chn@gmail.com, linux-kernel@vger.kernel.org, alison.wang@freescale.com List-Id: dri-devel@lists.freedesktop.org RG8gbm90IHNjaGVkdWxlIGEgdHJhbnNmZXIgb2YgbW9kZSBzZXR0aW5ncyBlYXJseS4gTW9kZXMg c2hvdWxkCmdldCBhcHBsaWVkIG9uIG9uIENSVEMgZW5hYmxlIHdoZXJlIHdlIGFsc28gZW5hYmxl IHRoZSBwaXhlbCBjbG9jay4KClNpZ25lZC1vZmYtYnk6IFN0ZWZhbiBBZ25lciA8c3RlZmFuQGFn bmVyLmNoPgotLS0KIGRyaXZlcnMvZ3B1L2RybS9mc2wtZGN1L2ZzbF9kY3VfZHJtX2NydGMuYyB8 IDIgLS0KIDEgZmlsZSBjaGFuZ2VkLCAyIGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2RyaXZl cnMvZ3B1L2RybS9mc2wtZGN1L2ZzbF9kY3VfZHJtX2NydGMuYyBiL2RyaXZlcnMvZ3B1L2RybS9m c2wtZGN1L2ZzbF9kY3VfZHJtX2NydGMuYwppbmRleCAzMzcxNjM1Li41YWQxZDY4IDEwMDY0NAot LS0gYS9kcml2ZXJzL2dwdS9kcm0vZnNsLWRjdS9mc2xfZGN1X2RybV9jcnRjLmMKKysrIGIvZHJp dmVycy9ncHUvZHJtL2ZzbC1kY3UvZnNsX2RjdV9kcm1fY3J0Yy5jCkBAIC0xMTYsOCArMTE2LDYg QEAgc3RhdGljIHZvaWQgZnNsX2RjdV9kcm1fY3J0Y19tb2RlX3NldF9ub2ZiKHN0cnVjdCBkcm1f Y3J0YyAqY3J0YykKIAkJICAgICBEQ1VfVEhSRVNIT0xEX0xTX0JGX1ZTKEJGX1ZTX1ZBTCkgfAog CQkgICAgIERDVV9USFJFU0hPTERfT1VUX0JVRl9ISUdIKEJVRl9NQVhfVkFMKSB8CiAJCSAgICAg RENVX1RIUkVTSE9MRF9PVVRfQlVGX0xPVyhCVUZfTUlOX1ZBTCkpOwotCXJlZ21hcF93cml0ZShm c2xfZGV2LT5yZWdtYXAsIERDVV9VUERBVEVfTU9ERSwKLQkJICAgICBEQ1VfVVBEQVRFX01PREVf UkVBRFJFRyk7CiAJcmV0dXJuOwogfQogCi0tIAoyLjEwLjAKCl9fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRl dmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9t YWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo=