From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48943) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1byroj-0002gH-4H for qemu-devel@nongnu.org; Mon, 24 Oct 2016 22:50:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1byrog-0006lo-2P for qemu-devel@nongnu.org; Mon, 24 Oct 2016 22:50:21 -0400 Date: Tue, 25 Oct 2016 12:13:20 +1100 From: David Gibson Message-ID: <20161025011320.GJ11052@umbus.fritz.box> References: <1477129610-31353-1-git-send-email-clg@kaod.org> <1477129610-31353-8-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="1ou9v+QBCNysIXaH" Content-Disposition: inline In-Reply-To: <1477129610-31353-8-git-send-email-clg@kaod.org> Subject: Re: [Qemu-devel] [PATCH v5 07/17] ppc/pnv: add XSCOM infrastructure List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org, Alexander Graf --1ou9v+QBCNysIXaH Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, Oct 22, 2016 at 11:46:40AM +0200, C=E9dric Le Goater wrote: > On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves > as a backbone to connect different units of the system. The host > firmware connects to the PIB through a bridge unit, the > Alter-Display-Unit (ADU), which gives him access to all the chiplets > on the PCB network (Pervasive Connect Bus), the PIB acting as the root > of this network. >=20 > XSCOM (serial communication) is the interface to the sideband bus > provided by the POWER8 pervasive unit to read and write to chiplets > resources. This is needed by the host firmware, OPAL and to a lesser > extent, Linux. This is among others how the PCI Host bridges get > configured at boot or how the LPC bus is accessed. >=20 > To represent the ADU of a real system, we introduce a specific > AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The > translation of an XSCOM address into a PCB register address is > slightly different between the P9 and the P8. This is handled before > the dispatch using a 8byte alignment for all. >=20 > To customize the device tree, a QOM InterfaceClass, PnvXScomInterface, > is provided with a populate() handler. The chip populates the device > tree by simply looping on its children. Therefore, each model needing > custom nodes should not forget to declare itself as a child at > instantiation time. >=20 > Based on previous work done by : > Benjamin Herrenschmidt >=20 > Signed-off-by: C=E9dric Le Goater Looks like xscom_complete() is still using current_cpu, which I've mentioned before. Apart from that; Reviewed-by: David Gibson > --- >=20 > Changes since v4: >=20 > - added helpers to initialize and map the chiplet XSCOM regions > in the XSCOM address space. This is to hide the '<< 3' shift. >=20 > Changes since v3: >=20 > - reworked the model to dispatch addresses to the memory regions > using pcb_addr << 3, which is a no-op for the P9. The benefit is > that all the address translation work can be done before dispatch > and the conversion handlers in the chip and in the xscom interface > are gone. > =20 > - removed the proxy PnnXscom object and extended the PnvChip object > with an address space for XSCOM and its associated memory region. > =20 > - changed the read/write handlers in the address space to use > address_space_stq() and address_space_ldq() > =20 > - introduced 'fake' default read/write handlers to handle 'core' > registers. We can add a real device model when more work needs to > be done under these. > =20 > - fixed an issue with the monitor doing read/write in the XSCOM > address space. When under the monitor, we don't have a cpu to > update the HMER SPR. That might need more work in the long term. > =20 > - introduced a xscom base field to hold the xscom base address as > it is different on P9 >=20 > - renamed the devnode() handler to populate() >=20 > Changes since v2: >=20 > - QOMified the model. > =20 > - all mappings in main memory space are now gathered in > pnv_chip_realize() as done on other architectures. > =20 > - removed XScomBus. The parenthood is established through the QOM > model > =20 > - replaced the XScomDevice with an InterfaceClass : PnvXScomInterface.= =20 > - introduced an XSCOM address space to dispatch accesses to the > chiplets >=20 > hw/ppc/Makefile.objs | 2 +- > hw/ppc/pnv.c | 25 ++++ > hw/ppc/pnv_xscom.c | 277 +++++++++++++++++++++++++++++++++++++++= ++++++ > include/hw/ppc/pnv.h | 15 +++ > include/hw/ppc/pnv_xscom.h | 56 +++++++++ > 5 files changed, 374 insertions(+), 1 deletion(-) > create mode 100644 hw/ppc/pnv_xscom.c > create mode 100644 include/hw/ppc/pnv_xscom.h >=20 > diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs > index f8c7d1db9ade..08c213c40684 100644 > --- a/hw/ppc/Makefile.objs > +++ b/hw/ppc/Makefile.objs > @@ -6,7 +6,7 @@ obj-$(CONFIG_PSERIES) +=3D spapr_hcall.o spapr_iommu.o sp= apr_rtas.o > obj-$(CONFIG_PSERIES) +=3D spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng= =2Eo > obj-$(CONFIG_PSERIES) +=3D spapr_cpu_core.o > # IBM PowerNV > -obj-$(CONFIG_POWERNV) +=3D pnv.o pnv_core.o > +obj-$(CONFIG_POWERNV) +=3D pnv.o pnv_xscom.o pnv_core.o > ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy) > obj-y +=3D spapr_pci_vfio.o > endif > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 3413107697d3..96ba36cc272d 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -33,6 +33,8 @@ > #include "qemu/cutils.h" > #include "qapi/visitor.h" > =20 > +#include "hw/ppc/pnv_xscom.h" > + > #include > =20 > #define FDT_MAX_SIZE 0x00100000 > @@ -219,6 +221,8 @@ static void powernv_populate_chip(PnvChip *chip, void= *fdt) > size_t typesize =3D object_type_get_instance_size(typename); > int i; > =20 > + pnv_xscom_populate(chip, fdt, 0); > + > for (i =3D 0; i < chip->nr_cores; i++) { > PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); > =20 > @@ -455,6 +459,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *= klass, void *data) > k->chip_cfam_id =3D 0x221ef04980000000ull; /* P8 Murano DD2.1 */ > k->cores_mask =3D POWER8E_CORE_MASK; > k->core_pir =3D pnv_chip_core_pir_p8; > + k->xscom_base =3D 0x003fc0000000000ull; > dc->desc =3D "PowerNV Chip POWER8E"; > } > =20 > @@ -475,6 +480,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) > k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */ > k->cores_mask =3D POWER8_CORE_MASK; > k->core_pir =3D pnv_chip_core_pir_p8; > + k->xscom_base =3D 0x003fc0000000000ull; > dc->desc =3D "PowerNV Chip POWER8"; > } > =20 > @@ -495,6 +501,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) > k->chip_cfam_id =3D 0x120d304980000000ull; /* P8 Naples DD1.0 */ > k->cores_mask =3D POWER8_CORE_MASK; > k->core_pir =3D pnv_chip_core_pir_p8; > + k->xscom_base =3D 0x003fc0000000000ull; > dc->desc =3D "PowerNV Chip POWER8NVL"; > } > =20 > @@ -515,6 +522,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) > k->chip_cfam_id =3D 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ > k->cores_mask =3D POWER9_CORE_MASK; > k->core_pir =3D pnv_chip_core_pir_p9; > + k->xscom_base =3D 0x00603fc00000000ull; > dc->desc =3D "PowerNV Chip POWER9"; > } > =20 > @@ -555,6 +563,14 @@ static void pnv_chip_core_sanitize(PnvChip *chip, Er= ror **errp) > } > } > =20 > +static void pnv_chip_init(Object *obj) > +{ > + PnvChip *chip =3D PNV_CHIP(obj); > + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); > + > + chip->xscom_base =3D pcc->xscom_base; > +} > + > static void pnv_chip_realize(DeviceState *dev, Error **errp) > { > PnvChip *chip =3D PNV_CHIP(dev); > @@ -569,6 +585,14 @@ static void pnv_chip_realize(DeviceState *dev, Error= **errp) > return; > } > =20 > + /* XSCOM bridge */ > + pnv_xscom_realize(chip, &error); > + if (error) { > + error_propagate(errp, error); > + return; > + } > + sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); > + > /* Cores */ > pnv_chip_core_sanitize(chip, &error); > if (error) { > @@ -628,6 +652,7 @@ static const TypeInfo pnv_chip_info =3D { > .name =3D TYPE_PNV_CHIP, > .parent =3D TYPE_SYS_BUS_DEVICE, > .class_init =3D pnv_chip_class_init, > + .instance_init =3D pnv_chip_init, > .class_size =3D sizeof(PnvChipClass), > .abstract =3D true, > }; > diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c > new file mode 100644 > index 000000000000..fcc71d335fc3 > --- /dev/null > +++ b/hw/ppc/pnv_xscom.c > @@ -0,0 +1,277 @@ > +/* > + * QEMU PowerPC PowerNV XSCOM bus > + * > + * Copyright (c) 2016, IBM Corporation. > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > +#include "qemu/osdep.h" > +#include "qapi/error.h" > +#include "hw/hw.h" > +#include "qemu/log.h" > +#include "sysemu/kvm.h" > +#include "target-ppc/cpu.h" > +#include "hw/sysbus.h" > + > +#include "hw/ppc/fdt.h" > +#include "hw/ppc/pnv_xscom.h" > +#include "hw/ppc/pnv.h" > + > +#include > + > +static void xscom_complete(uint64_t hmer_bits) > +{ > + CPUState *cs =3D current_cpu; I still think this should take a cpu parameter, moving the current_cpu invocation to the callers. > + > + /* > + * TODO: When the read/write comes from the monitor, we do not > + * have a cpu. > + */ > + if (cs) { > + PowerPCCPU *cpu =3D POWERPC_CPU(cs); > + CPUPPCState *env =3D &cpu->env; > + > + /* > + * TODO: Need a CPU helper to set HMER, also handle generation > + * of HMIs > + */ > + cpu_synchronize_state(cs); > + env->spr[SPR_HMER] |=3D hmer_bits; > + } > +} > + > +static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr) > +{ > + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); > + > + addr &=3D (PNV_XSCOM_SIZE - 1); > + if (pcc->chip_type =3D=3D PNV_CHIP_POWER9) { > + return addr >> 3; > + } else { > + return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); > + } > +} > + > +static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) > +{ > + switch (pcba) { > + case 0xf000f: > + return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id; > + case 0x1010c00: /* PIBAM FIR */ > + case 0x1010c03: /* PIBAM FIR MASK */ > + case 0x2020007: /* ADU stuff */ > + case 0x2020009: /* ADU stuff */ > + case 0x202000f: /* ADU stuff */ > + return 0; > + case 0x2013f00: /* PBA stuff */ > + case 0x2013f01: /* PBA stuff */ > + case 0x2013f02: /* PBA stuff */ > + case 0x2013f03: /* PBA stuff */ > + case 0x2013f04: /* PBA stuff */ > + case 0x2013f05: /* PBA stuff */ > + case 0x2013f06: /* PBA stuff */ > + case 0x2013f07: /* PBA stuff */ > + return 0; > + case 0x2013028: /* CAPP stuff */ > + case 0x201302a: /* CAPP stuff */ > + case 0x2013801: /* CAPP stuff */ > + case 0x2013802: /* CAPP stuff */ > + return 0; > + default: > + return -1; > + } > +} > + > +static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t v= al) > +{ > + /* We ignore writes to these */ > + switch (pcba) { > + case 0xf000f: /* chip id is RO */ > + case 0x1010c00: /* PIBAM FIR */ > + case 0x1010c01: /* PIBAM FIR */ > + case 0x1010c02: /* PIBAM FIR */ > + case 0x1010c03: /* PIBAM FIR MASK */ > + case 0x1010c04: /* PIBAM FIR MASK */ > + case 0x1010c05: /* PIBAM FIR MASK */ > + case 0x2020007: /* ADU stuff */ > + case 0x2020009: /* ADU stuff */ > + case 0x202000f: /* ADU stuff */ > + return true; > + default: > + return false; > + } > +} > + > +static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width) > +{ > + PnvChip *chip =3D opaque; > + uint32_t pcba =3D pnv_xscom_pcba(chip, addr); > + uint64_t val =3D 0; > + MemTxResult result; > + > + /* Handle some SCOMs here before dispatch */ > + val =3D xscom_read_default(chip, pcba); > + if (val !=3D -1) { > + goto complete; > + } > + > + val =3D address_space_ldq(&chip->xscom_as, pcba << 3, MEMTXATTRS_UNS= PECIFIED, > + &result); > + if (result !=3D MEMTX_OK) { > + qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%" > + HWADDR_PRIx " pcba=3D0x%08x\n", addr, pcba); > + xscom_complete(HMER_XSCOM_FAIL | HMER_XSCOM_DONE); > + return 0; > + } > + > +complete: > + xscom_complete(HMER_XSCOM_DONE); > + return val; > +} > + > +static void xscom_write(void *opaque, hwaddr addr, uint64_t val, > + unsigned width) > +{ > + PnvChip *chip =3D opaque; > + uint32_t pcba =3D pnv_xscom_pcba(chip, addr); > + MemTxResult result; > + > + /* Handle some SCOMs here before dispatch */ > + if (xscom_write_default(chip, pcba, val)) { > + goto complete; > + } > + > + address_space_stq(&chip->xscom_as, pcba << 3, val, MEMTXATTRS_UNSPEC= IFIED, > + &result); > + if (result !=3D MEMTX_OK) { > + qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%" > + HWADDR_PRIx " pcba=3D0x%08x data=3D0x%" PRIx64 "\n= ", > + addr, pcba, val); > + xscom_complete(HMER_XSCOM_FAIL | HMER_XSCOM_DONE); > + return; > + } > + > +complete: > + xscom_complete(HMER_XSCOM_DONE); > +} > + > +const MemoryRegionOps pnv_xscom_ops =3D { > + .read =3D xscom_read, > + .write =3D xscom_write, > + .valid.min_access_size =3D 8, > + .valid.max_access_size =3D 8, > + .impl.min_access_size =3D 8, > + .impl.max_access_size =3D 8, > + .endianness =3D DEVICE_BIG_ENDIAN, > +}; > + > +void pnv_xscom_realize(PnvChip *chip, Error **errp) > +{ > + SysBusDevice *sbd =3D SYS_BUS_DEVICE(chip); > + char *name; > + > + name =3D g_strdup_printf("xscom-%x", chip->chip_id); > + memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_op= s, > + chip, name, PNV_XSCOM_SIZE); > + sysbus_init_mmio(sbd, &chip->xscom_mmio); > + > + memory_region_init(&chip->xscom, OBJECT(chip), name, PNV_XSCOM_SIZE); > + address_space_init(&chip->xscom_as, &chip->xscom, name); > + g_free(name); > +} > + > +static const TypeInfo pnv_xscom_interface_info =3D { > + .name =3D TYPE_PNV_XSCOM_INTERFACE, > + .parent =3D TYPE_INTERFACE, > + .class_size =3D sizeof(PnvXScomInterfaceClass), > +}; > + > +static void pnv_xscom_register_types(void) > +{ > + type_register_static(&pnv_xscom_interface_info); > +} > + > +type_init(pnv_xscom_register_types) > + > +typedef struct ForeachPopulateArgs { > + void *fdt; > + int xscom_offset; > +} ForeachPopulateArgs; > + > +static int xscom_populate_child(Object *child, void *opaque) > +{ > + if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) { > + ForeachPopulateArgs *args =3D opaque; > + PnvXScomInterface *xd =3D PNV_XSCOM_INTERFACE(child); > + PnvXScomInterfaceClass *xc =3D PNV_XSCOM_INTERFACE_GET_CLASS(xd); > + > + if (xc->populate) { > + _FDT((xc->populate(xd, args->fdt, args->xscom_offset))); > + } > + } > + return 0; > +} > + > +static const char compat_p8[] =3D "ibm,power8-xscom\0ibm,xscom"; > +static const char compat_p9[] =3D "ibm,power9-xscom\0ibm,xscom"; > + > +int pnv_xscom_populate(PnvChip *chip, void *fdt, int root_offset) > +{ > + uint64_t reg[] =3D { cpu_to_be64(PNV_XSCOM_BASE(chip)), > + cpu_to_be64(PNV_XSCOM_SIZE) }; > + int xscom_offset; > + ForeachPopulateArgs args; > + char *name; > + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); > + > + name =3D g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0])); > + xscom_offset =3D fdt_add_subnode(fdt, root_offset, name); > + _FDT(xscom_offset); > + g_free(name); > + _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_= id))); > + _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1))); > + _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1))); > + _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg)))); > + > + if (pcc->chip_type =3D=3D PNV_CHIP_POWER9) { > + _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9, > + sizeof(compat_p9)))); > + } else { > + _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8, > + sizeof(compat_p8)))); > + } > + > + _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0))); > + > + args.fdt =3D fdt; > + args.xscom_offset =3D xscom_offset; > + > + object_child_foreach(OBJECT(chip), xscom_populate_child, &args); > + return 0; > +} > + > +void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion = *mr) > +{ > + memory_region_add_subregion(&chip->xscom, offset << 3, mr); > +} > + > +void pnv_xscom_region_init(MemoryRegion *mr, > + struct Object *owner, > + const MemoryRegionOps *ops, > + void *opaque, > + const char *name, > + uint64_t size) > +{ > + memory_region_init_io(mr, owner, ops, opaque, name, size << 3); > +} > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index cec869ce6b59..7db922e285c0 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -21,6 +21,7 @@ > =20 > #include "hw/boards.h" > #include "hw/sysbus.h" > +#include "hw/ppc/pnv_xscom.h" > =20 > #define TYPE_PNV_CHIP "powernv-chip" > #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) > @@ -48,6 +49,11 @@ typedef struct PnvChip { > uint32_t nr_cores; > uint64_t cores_mask; > void *cores; > + > + hwaddr xscom_base; > + MemoryRegion xscom_mmio; > + MemoryRegion xscom; > + AddressSpace xscom_as; > } PnvChip; > =20 > typedef struct PnvChipClass { > @@ -60,6 +66,8 @@ typedef struct PnvChipClass { > uint64_t chip_cfam_id; > uint64_t cores_mask; > =20 > + hwaddr xscom_base; > + > uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); > } PnvChipClass; > =20 > @@ -106,4 +114,11 @@ typedef struct PnvMachineState { > #define PNV_FDT_ADDR 0x01000000 > #define PNV_TIMEBASE_FREQ 512000000ULL > =20 > +/* > + * POWER8 MMIO base addresses > + */ > +#define PNV_XSCOM_SIZE 0x800000000ull > +#define PNV_XSCOM_BASE(chip) \ > + (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) > + > #endif /* _PPC_PNV_H */ > diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h > new file mode 100644 > index 000000000000..ee25ec455e3f > --- /dev/null > +++ b/include/hw/ppc/pnv_xscom.h > @@ -0,0 +1,56 @@ > +/* > + * QEMU PowerPC PowerNV XSCOM bus definitions > + * > + * Copyright (c) 2016, IBM Corporation. > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > +#ifndef _PPC_PNV_XSCOM_H > +#define _PPC_PNV_XSCOM_H > + > +#include "qom/object.h" > + > +typedef struct PnvChip PnvChip; > + > +typedef struct PnvXScomInterface { > + Object parent; > +} PnvXScomInterface; > + > +#define TYPE_PNV_XSCOM_INTERFACE "pnv-xscom-interface" > +#define PNV_XSCOM_INTERFACE(obj) \ > + OBJECT_CHECK(PnvXScomInterface, (obj), TYPE_PNV_XSCOM_INTERFACE) > +#define PNV_XSCOM_INTERFACE_CLASS(klass) \ > + OBJECT_CLASS_CHECK(PnvXScomInterfaceClass, (klass), \ > + TYPE_PNV_XSCOM_INTERFACE) > +#define PNV_XSCOM_INTERFACE_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(PnvXScomInterfaceClass, (obj), TYPE_PNV_XSCOM_INTE= RFACE) > + > +typedef struct PnvXScomInterfaceClass { > + InterfaceClass parent; > + int (*populate)(PnvXScomInterface *dev, void *fdt, int offset); > +} PnvXScomInterfaceClass; > + > +extern void pnv_xscom_realize(PnvChip *chip, Error **errp); > +extern int pnv_xscom_populate(PnvChip *chip, void *fdt, int offset); > + > +extern void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, > + MemoryRegion *mr); > +extern void pnv_xscom_region_init(MemoryRegion *mr, > + struct Object *owner, > + const MemoryRegionOps *ops, > + void *opaque, > + const char *name, > + uint64_t size); > + > +#endif /* _PPC_PNV_XSCOM_H */ --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --1ou9v+QBCNysIXaH Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJYDrGuAAoJEGw4ysog2bOSFrEP/3z0CrifQV7l4OZwIIY/5dPr /1ZWoMuF4SRPUIDZPgU3/fui+yEAaVMbMauUGPzyRha+wNTLDE6HGtCr+29h9D/h jeFE+5rYAn/Jlx6RTDPa787r0UVtxfEFAjcUFhdf7EGxX9gvHTdhtrpMnTCA+u7d BjqWzIIfR+7bfA+uoP7Ucb9AG/rPtOKAlAYVaMXolytm8sGvNv+yomC1vH3r48b/ Sh5RcNNIEuxT6z0dgYcWq3h/HnBgZc0hENAXCJbhLFsaS3+T+MtavxUhc2sOsYjW ZLyzxWGdoBo3dlYuXuuav6PDISvTYj1nbqjFmZaP7WonmXwPAPlXXiD2ZHDFVULf LOnTEqAR0Pi3UKznT25JrleTYTG1e/zWlPTptxtkn0m7KHGJ3JXwcH5aDMXEYheT VxDbFFqkoC59+/s25BroWHVyUghDIOWTJxNo+VcFIlZz9UaPe6PXGE/tTbp0h6nK NwN4/+we1dibqtBnni3mmZ5gWQGIQl599pI0gas0eYnsdSMr9xga31Dn4UTKBkct asDzEOA5aVU2AtD49IxV1+fgbJiLso9E6ag2Mf/C3JfESLbtBrgWlzbq+r6sMILw 4Txa9rfp4un7DlKxTcfE1gJ80UUH+RA5I803iOAn92IyjfU8vO2MF8wtE+C2vdIJ GvJj1tV4g8QlmQ3HK5gl =Nzjj -----END PGP SIGNATURE----- --1ou9v+QBCNysIXaH--