From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48928) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1byroi-0002gE-FO for qemu-devel@nongnu.org; Mon, 24 Oct 2016 22:50:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1byrog-0006mA-Qq for qemu-devel@nongnu.org; Mon, 24 Oct 2016 22:50:20 -0400 Date: Tue, 25 Oct 2016 12:14:50 +1100 From: David Gibson Message-ID: <20161025011450.GK11052@umbus.fritz.box> References: <1477129610-31353-1-git-send-email-clg@kaod.org> <1477129610-31353-9-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="lildS9pRFgpM/xzO" Content-Disposition: inline In-Reply-To: <1477129610-31353-9-git-send-email-clg@kaod.org> Subject: Re: [Qemu-devel] [PATCH v5 08/17] ppc/pnv: add XSCOM handlers to PnvCore List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org, Alexander Graf --lildS9pRFgpM/xzO Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, Oct 22, 2016 at 11:46:41AM +0200, C=E9dric Le Goater wrote: > Now that we are using real HW ids for the cores in PowerNV chips, we > can route the XSCOM accesses to them. We just need to attach a > specific XSCOM memory region to each core in the appropriate window > for the core number. >=20 > To start with, let's install the DTS (Digital Thermal Sensor) handlers > which should return 38=B0C for each core. >=20 > Signed-off-by: C=E9dric Le Goater Reviewed-by: David Gibson > --- >=20 > Changes since v4: >=20 > - used the helpers for the XSCOM region=20 >=20 > Changes since v3: >=20 > - moved to new XSCOM model > - kept the write op on the XSCOM memory region for later use >=20 > Changes since v2: >=20 > - added a XSCOM memory region to handle access to the EX core > registers =20 > - extended the PnvCore object with a XSCOM_INTERFACE so that we can > use pnv_xscom_pcba() and pnv_xscom_addr() to handle XSCOM address > translation. >=20 > hw/ppc/pnv.c | 4 ++++ > hw/ppc/pnv_core.c | 50 ++++++++++++++++++++++++++++++++++++++++= ++++++ > include/hw/ppc/pnv_core.h | 2 ++ > include/hw/ppc/pnv_xscom.h | 19 ++++++++++++++++++ > 4 files changed, 75 insertions(+) >=20 > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 96ba36cc272d..df55a89cb951 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -625,6 +625,10 @@ static void pnv_chip_realize(DeviceState *dev, Error= **errp) > object_property_set_bool(OBJECT(pnv_core), true, "realized", > &error_fatal); > object_unref(OBJECT(pnv_core)); > + > + /* Each core has an XSCOM MMIO region */ > + pnv_xscom_add_subregion(chip, PNV_XSCOM_EX_CORE_BASE(core_hwid), > + &PNV_CORE(pnv_core)->xscom_regs); > i++; > } > g_free(typename); > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index 04713caa3b24..2acda9637db5 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -19,6 +19,7 @@ > #include "qemu/osdep.h" > #include "sysemu/sysemu.h" > #include "qapi/error.h" > +#include "qemu/log.h" > #include "target-ppc/cpu.h" > #include "hw/ppc/ppc.h" > #include "hw/ppc/pnv.h" > @@ -63,6 +64,51 @@ static void powernv_cpu_init(PowerPCCPU *cpu, Error **= errp) > qemu_register_reset(powernv_cpu_reset, cpu); > } > =20 > +/* > + * These values are read by the PowerNV HW monitors under Linux > + */ > +#define PNV_XSCOM_EX_DTS_RESULT0 0x50000 > +#define PNV_XSCOM_EX_DTS_RESULT1 0x50001 > + > +static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr, > + unsigned int width) > +{ > + uint32_t offset =3D addr >> 3; > + uint64_t val =3D 0; > + > + /* The result should be 38 C */ > + switch (offset) { > + case PNV_XSCOM_EX_DTS_RESULT0: > + val =3D 0x26f024f023f0000ull; > + break; > + case PNV_XSCOM_EX_DTS_RESULT1: > + val =3D 0x24f000000000000ull; > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "Warning: reading reg=3D0x%" HWADDR_PRI= x, > + addr); > + } > + > + return val; > +} > + > +static void pnv_core_xscom_write(void *opaque, hwaddr addr, uint64_t val, > + unsigned int width) > +{ > + qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=3D0x%" HWADDR_PRIx, > + addr); > +} > + > +static const MemoryRegionOps pnv_core_xscom_ops =3D { > + .read =3D pnv_core_xscom_read, > + .write =3D pnv_core_xscom_write, > + .valid.min_access_size =3D 8, > + .valid.max_access_size =3D 8, > + .impl.min_access_size =3D 8, > + .impl.max_access_size =3D 8, > + .endianness =3D DEVICE_BIG_ENDIAN, > +}; > + > static void pnv_core_realize_child(Object *child, Error **errp) > { > Error *local_err =3D NULL; > @@ -118,6 +164,10 @@ static void pnv_core_realize(DeviceState *dev, Error= **errp) > goto err; > } > } > + > + snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); > + pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), &pnv_core_xscom_= ops, > + pc, name, PNV_XSCOM_EX_CORE_SIZE); > return; > =20 > err: > diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h > index a151e281c017..2955a41c901f 100644 > --- a/include/hw/ppc/pnv_core.h > +++ b/include/hw/ppc/pnv_core.h > @@ -36,6 +36,8 @@ typedef struct PnvCore { > /*< public >*/ > void *threads; > uint32_t pir; > + > + MemoryRegion xscom_regs; > } PnvCore; > =20 > typedef struct PnvCoreClass { > diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h > index ee25ec455e3f..5da6e92e698c 100644 > --- a/include/hw/ppc/pnv_xscom.h > +++ b/include/hw/ppc/pnv_xscom.h > @@ -41,6 +41,25 @@ typedef struct PnvXScomInterfaceClass { > int (*populate)(PnvXScomInterface *dev, void *fdt, int offset); > } PnvXScomInterfaceClass; > =20 > +/* > + * Layout of the XSCOM PCB addresses of EX core 1 > + * > + * GPIO 0x1100xxxx > + * SCOM 0x1101xxxx > + * OHA 0x1102xxxx > + * CLOCK CTL 0x1103xxxx > + * FIR 0x1104xxxx > + * THERM 0x1105xxxx > + * 0x1106xxxx > + * .. > + * 0x110Exxxx > + * PCB SLAVE 0x110Fxxxx > + */ > + > +#define PNV_XSCOM_EX_BASE 0x10000000 > +#define PNV_XSCOM_EX_CORE_BASE(i) (PNV_XSCOM_EX_BASE | (((uint64_t)i) <<= 24)) > +#define PNV_XSCOM_EX_CORE_SIZE 0x100000 > + > extern void pnv_xscom_realize(PnvChip *chip, Error **errp); > extern int pnv_xscom_populate(PnvChip *chip, void *fdt, int offset); > =20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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