From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43878) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bz3YX-0001pW-6N for qemu-devel@nongnu.org; Tue, 25 Oct 2016 11:22:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bz3YT-0008Gl-Jg for qemu-devel@nongnu.org; Tue, 25 Oct 2016 11:22:25 -0400 Received: from mail-by2nam03on0041.outbound.protection.outlook.com ([104.47.42.41]:24105 helo=NAM03-BY2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1bz3YT-0008GG-7r for qemu-devel@nongnu.org; Tue, 25 Oct 2016 11:22:21 -0400 Date: Tue, 25 Oct 2016 14:47:32 +0200 From: "Edgar E. Iglesias" Message-ID: <20161025124732.GT32180@toto> References: <1477378140-2670-1-git-send-email-ppandit@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH] char: cadence: correct reset value for baud rate registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: P J P , Qemu Developers , qemu-arm , Prasad J Pandit , Alistair Francis On Tue, Oct 25, 2016 at 01:19:28PM +0100, Peter Maydell wrote: > On 25 October 2016 at 07:49, P J P wrote: > > From: Prasad J Pandit > > > > The Cadence UART device emulator stores 'baud rate generator' > > and 'baud rate divider' values, used in computing speed, in two > > registers. The device specification defines their range and > > their reset value. Use their correct value when resetting the > > device in cadence_uart_reset. > > > > Signed-off-by: Prasad J Pandit > > --- > > hw/char/cadence_uart.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c > > index c176446..b8d4c28 100644 > > --- a/hw/char/cadence_uart.c > > +++ b/hw/char/cadence_uart.c > > @@ -471,7 +471,8 @@ static void cadence_uart_reset(DeviceState *dev) > > s->r[R_IMR] = 0; > > s->r[R_CISR] = 0; > > s->r[R_RTRIG] = 0x00000020; > > - s->r[R_BRGR] = 0x0000000F; > > + s->r[R_BRGR] = 0x0000028B; > > + s->r[R_BDIV] = 0x0000000F; > > s->r[R_TTRIG] = 0x00000020; > > > > uart_rx_reset(s); > > -- > > 2.7.4 > > I'm going to wait for a review/ack from one of the Xilinx folk > before putting this in target-arm.next. Reviewed-by: Edgar E. Iglesias Best regards, Edgar