From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH v3 03/11] clk: qcom: handle alpha PLLs with 16bit alpha val registers Date: Wed, 2 Nov 2016 14:51:46 -0700 Message-ID: <20161102215146.GO16026@codeaurora.org> References: <1475138152-859-1-git-send-email-rnayak@codeaurora.org> <1475138152-859-4-git-send-email-rnayak@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1475138152-859-4-git-send-email-rnayak@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: Rajendra Nayak Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, tdas@codeaurora.org List-Id: linux-arm-msm@vger.kernel.org On 09/29, Rajendra Nayak wrote: > Some alpha PLLs have support for only a 16bit programable Alpha Value > (as against the default 40bits). Add a flag to handle the 16bit alpha > registers > > Signed-off-by: Rajendra Nayak > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project