From: Borislav Petkov <bp@suse.de>
To: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
x86@kernel.org, dave.hansen@linux.intel.com,
lukasz.daniluk@intel.com, james.h.cownie@intel.com,
jacob.jun.pan@intel.com, Piotr.Luc@intel.com,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit
Date: Thu, 3 Nov 2016 15:54:46 +0100 [thread overview]
Message-ID: <20161103145446.cwcljsbwhc2nvhs2@pd.tnic> (raw)
In-Reply-To: <1477995290-25079-2-git-send-email-grzegorz.andrejczuk@intel.com>
On Tue, Nov 01, 2016 at 11:14:47AM +0100, Grzegorz Andrejczuk wrote:
> Intel Xeon Phi x200 (codenamed Knights Landing) allows to enable
> MONITOR and MWAIT instructions outside of ring 0.
>
> The feature is controlled by MSR MISC_FEATURE_ENABLES (0x140).
> Setting bit 1 of this register enables it, so MONITOR and MWAIT
> instructions do not cause invalid-opcode exceptions when invoked
> outside of ring 0.
> The feature MSR is not yet documented in the SDM. Here is
> the relevant documentation:
>
> Hex Dec Name Scope
> 140H 320 MISC_FEATURE_ENABLES Thread
> 0 Reserved
> 1 if set to 1, the MONITOR and MWAIT instructions do not
> cause invalid-opcode exceptions when executed with CPL > 0
> or in virtual-8086 mode. If MWAIT is executed when CPL > 0
> or in virtual-8086 mode, and if EAX indicates a C-state
> other than C0 or C1, the instruction operates as if EAX
> indicated the C-state C1.
> 63:2 Reserved
>
> Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
> ---
> arch/x86/include/asm/msr-index.h | 5 +++++
> 1 file changed, 5 insertions(+)
Reviewed-by: Borislav Petkov <bp@suse.de>
--
Regards/Gruss,
Boris.
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
--
next prev parent reply other threads:[~2016-11-03 14:55 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-01 10:14 [PATCH v8: 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk
2016-11-01 10:14 ` [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit Grzegorz Andrejczuk
2016-11-03 14:54 ` Borislav Petkov [this message]
2016-11-03 17:00 ` Thomas Gleixner
2016-11-04 6:47 ` Andrejczuk, Grzegorz
2016-11-07 20:48 ` Thomas Gleixner
2016-11-01 10:14 ` [PATCH v8: 2/4] x86/elf: Use HWCAP2 to expose ring 3 MWAIT Grzegorz Andrejczuk
2016-11-01 10:14 ` [PATCH v8: 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Grzegorz Andrejczuk
2016-11-03 14:56 ` Borislav Petkov
2016-11-03 16:01 ` [PATCH v8 " Grzegorz Andrejczuk
2016-11-01 10:14 ` [PATCH v8: 4/4] x86/cpufeatures: Handle RING3MWAIT on Xeon Phi models Grzegorz Andrejczuk
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