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Date: Fri, 11 Nov 2016 21:05:00 +0100
From: Peter Zijlstra <peterz@infradead.org>
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Subject: Re: [kernel-hardening] Re: [RFC v4 PATCH 00/13] HARDENED_ATOMIC
To: Mark Rutland <mark.rutland@arm.com>
Cc: kernel-hardening@lists.openwall.com, Will Deacon <will.deacon@arm.com>, Greg KH <gregkh@linuxfoundation.org>, David Windsor <dave@progbits.org>, Elena Reshetova <elena.reshetova@intel.com>, Arnd Bergmann <arnd@arndb.de>, Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <h.peter.anvin@intel.com>
List-ID: <kernel-hardening.lists.openwall.com>

On Fri, Nov 11, 2016 at 06:31:18PM +0000, Mark Rutland wrote:
> On Fri, Nov 11, 2016 at 09:43:00AM -0800, Kees Cook wrote:
> > (And now Greg went missing from the reply? Re-added...)
> > 
> > On Thu, Nov 10, 2016 at 11:50 PM, David Windsor <dave@progbits.org> wrote:
> > > On Thu, Nov 10, 2016 at 6:38 PM, Greg KH <gregkh@linuxfoundation.org> wrote:
> > >> On Thu, Nov 10, 2016 at 03:15:44PM -0800, Kees Cook wrote:
> 
> > As far as refcount_t is concerned, I worry using cmpxchg will be too
> > costly, but it's worth benchmarking.
> 
> If that does turn out to be a problem, we could allow architectures to
> provide their own implementations of the API, with a generic fallback
> otherwise, as we do for other features.

Note that only LL/SC archs can do somewhat better. x86/s390/sparc64 etc
al must use cmpxchg, there's just no other way to get an actual atomic
inc/dec with over/under-flow detection.

The proposed x86 implementation is non-atomic and therefore a complete
nonstarter.