From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933530AbcKOMKw (ORCPT ); Tue, 15 Nov 2016 07:10:52 -0500 Received: from 8bytes.org ([81.169.241.247]:35331 "EHLO theia.8bytes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932810AbcKOMKs (ORCPT ); Tue, 15 Nov 2016 07:10:48 -0500 Date: Tue, 15 Nov 2016 13:10:35 +0100 From: Joerg Roedel To: Tom Lendacky Cc: linux-arch@vger.kernel.org, linux-efi@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, iommu@lists.linux-foundation.org, Rik van Riel , Radim =?utf-8?B?S3LEjW3DocWZ?= , Arnd Bergmann , Jonathan Corbet , Matt Fleming , Konrad Rzeszutek Wilk , Paolo Bonzini , Larry Woodman , Ingo Molnar , Borislav Petkov , Andy Lutomirski , "H. Peter Anvin" , Andrey Ryabinin , Alexander Potapenko , Thomas Gleixner , Dmitry Vyukov Subject: Re: [RFC PATCH v3 04/20] x86: Handle reduction in physical address size with SME Message-ID: <20161115121035.GD24857@8bytes.org> References: <20161110003426.3280.2999.stgit@tlendack-t1.amdoffice.net> <20161110003513.3280.12104.stgit@tlendack-t1.amdoffice.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20161110003513.3280.12104.stgit@tlendack-t1.amdoffice.net> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Nov 09, 2016 at 06:35:13PM -0600, Tom Lendacky wrote: > +/* > + * AMD Secure Memory Encryption (SME) can reduce the size of the physical > + * address space if it is enabled, even if memory encryption is not active. > + * Adjust x86_phys_bits if SME is enabled. > + */ > +static void phys_bits_adjust(struct cpuinfo_x86 *c) > +{ Better call this function amd_sme_phys_bits_adjust(). This name makes it clear at the call-site why it is there and what it does. > + u32 eax, ebx, ecx, edx; > + u64 msr; > + > + if (c->x86_vendor != X86_VENDOR_AMD) > + return; > + > + if (c->extended_cpuid_level < 0x8000001f) > + return; > + > + /* Check for SME feature */ > + cpuid(0x8000001f, &eax, &ebx, &ecx, &edx); > + if (!(eax & 0x01)) > + return; Maybe add a comment here why you can't use cpu_has (yet). From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joerg Roedel Subject: Re: [RFC PATCH v3 04/20] x86: Handle reduction in physical address size with SME Date: Tue, 15 Nov 2016 13:10:35 +0100 Message-ID: <20161115121035.GD24857@8bytes.org> References: <20161110003426.3280.2999.stgit@tlendack-t1.amdoffice.net> <20161110003513.3280.12104.stgit@tlendack-t1.amdoffice.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <20161110003513.3280.12104.stgit-qCXWGYdRb2BnqfbPTmsdiZQ+2ll4COg0XqFh9Ls21Oc@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Tom Lendacky Cc: linux-efi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Radim =?utf-8?B?S3LEjW3DocWZ?= , Matt Fleming , x86-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org, Alexander Potapenko , "H. Peter Anvin" , Larry Woodman , linux-arch-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Jonathan Corbet , linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, kasan-dev-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Ingo Molnar , Andrey Ryabinin , Rik van Riel , Arnd Bergmann , Borislav Petkov , Andy Lutomirski , Thomas Gleixner , Dmitry Vyukov , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, Paolo Bonzini List-Id: linux-efi@vger.kernel.org On Wed, Nov 09, 2016 at 06:35:13PM -0600, Tom Lendacky wrote: > +/* > + * AMD Secure Memory Encryption (SME) can reduce the size of the physical > + * address space if it is enabled, even if memory encryption is not active. > + * Adjust x86_phys_bits if SME is enabled. > + */ > +static void phys_bits_adjust(struct cpuinfo_x86 *c) > +{ Better call this function amd_sme_phys_bits_adjust(). This name makes it clear at the call-site why it is there and what it does. > + u32 eax, ebx, ecx, edx; > + u64 msr; > + > + if (c->x86_vendor != X86_VENDOR_AMD) > + return; > + > + if (c->extended_cpuid_level < 0x8000001f) > + return; > + > + /* Check for SME feature */ > + cpuid(0x8000001f, &eax, &ebx, &ecx, &edx); > + if (!(eax & 0x01)) > + return; Maybe add a comment here why you can't use cpu_has (yet). From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f72.google.com (mail-wm0-f72.google.com [74.125.82.72]) by kanga.kvack.org (Postfix) with ESMTP id 010476B0277 for ; Tue, 15 Nov 2016 07:10:48 -0500 (EST) Received: by mail-wm0-f72.google.com with SMTP id i131so49729426wmf.3 for ; Tue, 15 Nov 2016 04:10:47 -0800 (PST) Received: from theia.8bytes.org (8bytes.org. [81.169.241.247]) by mx.google.com with ESMTPS id p21si2799506wmb.29.2016.11.15.04.10.46 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Nov 2016 04:10:46 -0800 (PST) Date: Tue, 15 Nov 2016 13:10:35 +0100 From: Joerg Roedel Subject: Re: [RFC PATCH v3 04/20] x86: Handle reduction in physical address size with SME Message-ID: <20161115121035.GD24857@8bytes.org> References: <20161110003426.3280.2999.stgit@tlendack-t1.amdoffice.net> <20161110003513.3280.12104.stgit@tlendack-t1.amdoffice.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20161110003513.3280.12104.stgit@tlendack-t1.amdoffice.net> Sender: owner-linux-mm@kvack.org List-ID: To: Tom Lendacky Cc: linux-arch@vger.kernel.org, linux-efi@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, iommu@lists.linux-foundation.org, Rik van Riel , Radim =?utf-8?B?S3LEjW3DocWZ?= , Arnd Bergmann , Jonathan Corbet , Matt Fleming , Konrad Rzeszutek Wilk , Paolo Bonzini , Larry Woodman , Ingo Molnar , Borislav Petkov , Andy Lutomirski , "H. Peter Anvin" , Andrey Ryabinin , Alexander Potapenko , Thomas Gleixner , Dmitry Vyukov On Wed, Nov 09, 2016 at 06:35:13PM -0600, Tom Lendacky wrote: > +/* > + * AMD Secure Memory Encryption (SME) can reduce the size of the physical > + * address space if it is enabled, even if memory encryption is not active. > + * Adjust x86_phys_bits if SME is enabled. > + */ > +static void phys_bits_adjust(struct cpuinfo_x86 *c) > +{ Better call this function amd_sme_phys_bits_adjust(). This name makes it clear at the call-site why it is there and what it does. > + u32 eax, ebx, ecx, edx; > + u64 msr; > + > + if (c->x86_vendor != X86_VENDOR_AMD) > + return; > + > + if (c->extended_cpuid_level < 0x8000001f) > + return; > + > + /* Check for SME feature */ > + cpuid(0x8000001f, &eax, &ebx, &ecx, &edx); > + if (!(eax & 0x01)) > + return; Maybe add a comment here why you can't use cpu_has (yet). -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. 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