From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Fri, 25 Nov 2016 23:32:30 +0100 Subject: [U-Boot] [PATCH 09/14] gpio: Add JZ47xx GPIO driver In-Reply-To: <20161125223235.3434-1-marex@denx.de> References: <20161125223235.3434-1-marex@denx.de> Message-ID: <20161125223235.3434-9-marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Paul Burton Add primitive GPIO controller driver for the JZ47xx SoC. Signed-off-by: Marek Vasut Cc: Daniel Schwierzeck Cc: Paul Burton --- drivers/gpio/Kconfig | 8 +++++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-jz47xx.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 88 insertions(+) create mode 100644 drivers/gpio/gpio-jz47xx.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8d9ab52..4515883 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -221,4 +221,12 @@ config MPC85XX_GPIO The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well. + +config JZ47XX_GPIO + bool "Ingenic JZ47xx GPIO driver" + depends on ARCH_JZ47XX + default y + help + Supports GPIO access on Ingenic JZ47xx SoCs. + endmenu diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 8939226..e562022 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -58,3 +58,4 @@ obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o obj-$(CONFIG_MSM_GPIO) += msm_gpio.o obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o +obj-$(CONFIG_JZ47XX_GPIO) += gpio-jz47xx.o diff --git a/drivers/gpio/gpio-jz47xx.c b/drivers/gpio/gpio-jz47xx.c new file mode 100644 index 0000000..210120d --- /dev/null +++ b/drivers/gpio/gpio-jz47xx.c @@ -0,0 +1,79 @@ +/* + * Ingenic JZ47xx GPIO + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +int gpio_get_value(unsigned gpio) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + int port = gpio / 32; + int pin = gpio % 32; + + return readl(gpio_regs + GPIO_PXPIN(port)) & BIT(pin); +} + +int gpio_set_value(unsigned gpio, int value) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + int port = gpio / 32; + int pin = gpio % 32; + + if (value) + writel(BIT(pin), gpio_regs + GPIO_PXPAT0S(port)); + else + writel(BIT(pin), gpio_regs + GPIO_PXPAT0C(port)); + + return 0; +} + +int gpio_direction_input(unsigned gpio) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + int port = gpio / 32; + int pin = gpio % 32; + + writel(BIT(pin), gpio_regs + GPIO_PXINTC(port)); + writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port)); + writel(BIT(pin), gpio_regs + GPIO_PXPAT1S(port)); + + return 0; +} + +int gpio_direction_output(unsigned gpio, int value) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + int port = gpio / 32; + int pin = gpio % 32; + + writel(BIT(pin), gpio_regs + GPIO_PXINTC(port)); + writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port)); + writel(BIT(pin), gpio_regs + GPIO_PXPAT1C(port)); + + gpio_set_value(gpio, value); + + return 0; +} + +int gpio_request(unsigned gpio, const char *label) +{ + int port = gpio / 32; + + if (port >= 6) + return -EINVAL; + + return 0; +} + +int gpio_free(unsigned gpio) +{ + return 0; +} -- 2.10.2