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From: Yi Sun <yi.y.sun@linux.intel.com>
To: Dario Faggioli <dario.faggioli@citrix.com>
Cc: wei.liu2@citrix.com, he.chen@linux.intel.com,
	andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com,
	jbeulich@suse.com, xen-devel@lists.xenproject.org,
	chao.p.peng@linux.intel.com
Subject: Re: [PATCH v3 01/15] docs: L2 Cache Allocation Technology (CAT) feature document.
Date: Tue, 29 Nov 2016 13:20:24 +0800	[thread overview]
Message-ID: <20161129052024.GC7435@yi.y.sun> (raw)
In-Reply-To: <1480094357.2712.177.camel@citrix.com>

On 16-11-25 18:19:17, Dario Faggioli wrote:
> On Fri, 2016-11-11 at 16:33 -0500, Konrad Rzeszutek Wilk wrote:
> > On Tue, Oct 25, 2016 at 11:40:49AM +0800, Yi Sun wrote:
> > > --- /dev/null
> > > +++ b/docs/features/l2_cat.pandoc
> > > @@ -0,0 +1,314 @@
> > > +% Intel L2 Cache Allocation Technology (L2 CAT) Feature
> > > +% Revision 2.0
> > > +
> > > +\clearpage
> > > +
> > > +# Basics
> > > +
> > > +---------------- -----------------------------------------------
> > > -----
> > > +         Status: **Tech Preview**
> > > +
> > > +Architecture(s): Intel x86
> > > +
> > > +   Component(s): Hypervisor, toolstack
> > > +
> > > +       Hardware: Atom codename Goldmont and beyond
> >
> Atom codename Goldmont and beyond CPUs
> 
> It may sound obvious, but I'd explicitly add that bit.
> 
Ok, thanks!

> > > +---------------- -----------------------------------------------
> > > -----
> > > +
> > > +# Overview
> > > +
> > > +L2 CAT allows an OS or Hypervisor/VMM to control allocation of a
> > 
> > Could you define CAT?
> > 
> > > 
> > > +CPU's shared L2 cache based on application priority or Class of
> > > Service
> > > +(COS). Each CLOS is configured using capacity bitmasks (CBM) which
> > > +represent cache capacity and indicate the degree of overlap and
> > > +isolation between classes. Once L2 CAT is configured, the
> > > processor
> > > +allows access to portions of L2 cache according to the established
> > > +class of service (COS).
> > > +
> > > +# Technical information
> > > +
> > > +L2 CAT is a member of Intel PSR features and part of CAT, it
> > > shares
> > 
> > Could you define 'PSR' here? Usually when you introduce an acronym
> > you do something like:
> > 
> > Intel Problem Solver Resolver (PSR)
> > 
> Wasn't it the 'Intel Probabilistic Silicon Reorganizer' ? :-D :-D
> 
It is 'Intel Platform Shared Resource' indeed. :-)

> > and that makes it easy for folks to map the acronym to the full
> > feature.
> > 
> Actually, given the density of acronyms, I'd say it would be good to
> add a "## Terminology" section at the top, and define all of them there
> upfront.
> 
Thanks! I will add this section.

> Also, I see that you're meaning this to be committed in tree and act as
> the L2 CAT feature document. I know that you've been asked to put it in
> tree (although, the request was for docs/misc/) and I think it's good
> to have a feature document for L2 CAT.
> 
> It contains a lot more technical details than the other (few) feature
> documents we have in tree right now. Personally, I'm fine with that,
> but I'd say that at least try to filling these sections would be
> important:
> 
> (from docs/features/template.pandoc)
> 
>   # Limitations
>   Information concerning incompatibilities with other features or
>   hardware combinations.
> 
>   # Testing
>   Information concerning how to properly test changes affecting this 
>   feature.
> 
>   # Areas for improvement
>   List of enhancements which could be undertaken, e.g. to improve the
>   feature itself, or improve interaction with other features.
> 
>   # Known issues
>   List of known issues or bugs.  For tech preview or experimental
>   features, this section must contain the list of items needing fixing
>   for its status to be upgraded.
> 
Thanks! Will try to add these sections.

> Also, it would be really good to have similar documents for the other
> PSR features we have upstream already (perhaps finding a way for not
> duplicating all the common information).
> 
Besides L2 CAT, there are L3 CAT and CDP features for allocation tech.
Also, there are CMT/MBM features for monitoring tech. We will discuss
these to check if we can add these feature documents step by step.

> Thanks and Regards,
> Dario
> -- 
> <<This happens because I choose it to happen!>> (Raistlin Majere)
> -----------------------------------------------------------------
> Dario Faggioli, Ph.D, http://about.me/dario.faggioli
> Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK)



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  reply	other threads:[~2016-11-29  5:20 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-25  3:40 [PATCH v3 00/15] Enable L2 Cache Allocation Technology Yi Sun
2016-10-25  3:40 ` [PATCH v3 01/15] docs: L2 Cache Allocation Technology (CAT) feature document Yi Sun
2016-10-25 13:37   ` Jan Beulich
2016-10-26  1:01     ` Yi Sun
2016-10-30 15:51   ` Meng Xu
2016-11-01  4:40     ` Yi Sun
2016-11-11 21:33   ` Konrad Rzeszutek Wilk
2016-11-14  2:15     ` Yi Sun
2016-11-25 17:19     ` Dario Faggioli
2016-11-29  5:20       ` Yi Sun [this message]
2016-11-29 12:25         ` Dario Faggioli
2016-11-25 17:39   ` Dario Faggioli
2016-11-29  4:52     ` Yi Sun
2016-11-29 12:22       ` Dario Faggioli
2016-11-30  1:42         ` Yi Sun
2016-10-25  3:40 ` [PATCH v3 02/15] x86: refactor psr: Split 'ref' out Yi Sun
2016-11-25 15:19   ` Jan Beulich
2016-10-25  3:40 ` [PATCH v3 03/15] x86: refactor psr: Remove 'struct psr_cat_cbm' Yi Sun
2016-11-25 15:45   ` Jan Beulich
2016-10-25  3:40 ` [PATCH v3 04/15] x86: refactor psr: Encapsulate 'cbm_len' and 'cbm_max' Yi Sun
2016-11-25 16:27   ` Jan Beulich
2016-11-25 16:57     ` Jan Beulich
2016-11-29  4:38       ` Yi Sun
2016-11-29  9:43         ` Jan Beulich
2016-11-30  9:08           ` Yi Sun
2016-11-30  9:42             ` Jan Beulich
2016-11-30 10:22               ` Yi Sun
2016-10-25  3:40 ` [PATCH v3 05/15] x86: refactor psr: Use 'feat_mask' to record featues enabled Yi Sun
2016-11-25 16:36   ` Jan Beulich
2016-10-25  3:40 ` [PATCH v3 06/15] x86: refactor psr: Create feature list Yi Sun
2016-10-25  3:40 ` [PATCH v3 07/15] x86: refactor psr: Implement feature operations structure Yi Sun
2016-10-25  3:40 ` [PATCH v3 08/15] x86: refactor psr: Implement get hw info callback function Yi Sun
2016-10-25  3:40 ` [PATCH v3 09/15] x86: refactor psr: Implement get value " Yi Sun
2016-10-25  3:40 ` [PATCH v3 10/15] x86: refactor psr: Implement function to get the max cos_max Yi Sun
2016-10-25  3:40 ` [PATCH v3 11/15] x86: refactor psr: Implement set value callback function Yi Sun
2016-10-25  3:41 ` [PATCH v3 12/15] x86: Implement L2 CAT in psr.c Yi Sun
2016-10-25  3:41 ` [PATCH v3 13/15] x86: Add L2 CAT interfaces in domctl Yi Sun
2016-10-25  3:41 ` [PATCH v3 14/15] x86: Add L2 CAT interfaces in sysctl Yi Sun
2016-10-25  3:41 ` [PATCH v3 15/15] tools & docs: add L2 CAT support in tools and docs Yi Sun
2016-11-09  1:28 ` [PATCH v3 00/15] Enable L2 Cache Allocation Technology Yi Sun
2016-11-09  8:37   ` Jan Beulich
2016-11-10  1:56     ` Yi Sun

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